Planar Double-Gate Transistor: From technology to circuit

by Amara Amara (Editor), Olivier Rozeau (Editor)

Overview

Until the 1990s, the reduction of the minimum feature sizes used to fabricate in- grated circuits, called “scaling”, has highlighted serious advantages as integration density, speed, power consumption, functionality and cost. Direct consequence was the decrease of cost-per-function, so the electronic productivity has largely progressed in this period. Another usually cited trend is the evolution of the in- gration density as expressed by the well-know Moore’s Law in 1975: the number of devices per chip doubles every 2 years. This evolution has allowed improving significantly the circuit complexity, offering a great computing power in the case of microprocessor, for example. However, since few years, significant issues appeared such as the increase of the circuit heating, device complexity, variability and difficulties to improve the integration density. These new trends generate an important growth in development and production costs. Though is it, since 40 years, the evolution of the microelectronics always f- lowed the Moore’s law and each difficulty has found a solution.

Product Details

ISBN-13:	9781402093272
Publisher:	Springer Netherlands
Publication date:	01/30/2009
Edition description:	2009
Pages:	211
Product dimensions:	6.40(w) x 9.30(h) x 2.40(d)

Table of Contents

Multiple Gate Technologies.- Compact Modeling of Independent Double-Gate MOSFET: A Physical Approach.- Compact Modeling of Double Gate MOSFET for IC Design.- Low Frequency Noise in Double-Gate SOI CMOS Devices.- Analog Circuit Design.- Logic Circuit Design with DGMOS Devices.- SRAM Circuit Design.