Power-Aware Computer Systems: Third International Workshop, PACS 2003, San Diego, CA, USA, December 1, 2003, Revised Papers / Edition 1

Power-Aware Computer Systems: Third International Workshop, PACS 2003, San Diego, CA, USA, December 1, 2003, Revised Papers / Edition 1

by Babak Falsafi
     
 

This book contributes the thoroughly refereed post-proceedings of the Third International Workshop on Power-Aware Computer Systems, PACS 2003, held in San Diego, CA, USA in December 2003.

The 14 revised full papers presented were carefully selected during two rounds of reviewing and improvement from 43 submissions. The papers span a wide spectrum of topics in

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Overview

This book contributes the thoroughly refereed post-proceedings of the Third International Workshop on Power-Aware Computer Systems, PACS 2003, held in San Diego, CA, USA in December 2003.

The 14 revised full papers presented were carefully selected during two rounds of reviewing and improvement from 43 submissions. The papers span a wide spectrum of topics in power-aware systems; they are organized in topical sections on compilers, embedded systems, microarchitectures, and cache and memory systems.

Product Details

ISBN-13:
9783540240310
Publisher:
Springer Berlin Heidelberg
Publication date:
02/14/2005
Series:
Lecture Notes in Computer Science Series, #3164
Edition description:
2005
Pages:
215
Product dimensions:
9.21(w) x 6.14(h) x 0.49(d)

Meet the Author

Table of Contents

Compilers.- Runtime Biased Pointer Reuse Analysis and Its Application to Energy Efficiency.- Inter-program Compilation for Disk Energy Reduction.- Embedded Systems.- Energy Consumption in Mobile Devices: Why Future Systems Need Requirements–Aware Energy Scale-Down.- Efficient Scratchpad Allocation Algorithms for Energy Constrained Embedded Systems.- Online Prediction of Battery Lifetime for Embedded and Mobile Devices.- Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture.- Heterogeneous Wireless Network Management.- Microarchitectural Techniques.- “Look It Up” or “Do the Math”: An Energy, Area, and Timing Analysis of Instruction Reuse and Memoization.- CPU Packing for Multiprocessor Power Reduction.- Exploring the Potential of Architecture-Level Power Optimizations.- Coupled Power and Thermal Simulation with Active Cooling.- Cache and Memory Systems.- The Synergy Between Power-Aware Memory Systems and Processor Voltage Scaling.- Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches.- PARROT: Power Awareness Through Selective Dynamically Optimized Traces.

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