Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard

by Nicola Nicolici, Bashir M. Al-Hashimi

Overview

Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density.

Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.

Product Details

ISBN-13:	9781402072352
Publisher:	Springer US
Publication date:	02/28/2003
Series:	Frontiers in Electronic Testing , #22
Edition description:	2003
Pages:	178
Product dimensions:	8.27(w) x 11.69(h) x 0.02(d)

Table of Contents

Design and Test of Digital Integrated Circuits.- Power Dissipation During Test.- Approaches to Handle Test Power.- Power Minimization Based on Best Primary Input Change Time.- Test Power Minimization Using Multiple Scan Chains.- Power-conscious Test Synthesis and Scheduling.- Power Profile Manipulation.- Conclusion.