Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog / Edition 2

Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog / Edition 2

by Lionel Bening, Harry D. Foster, Harry Foster
     
 

ISBN-10: 0792373685

ISBN-13: 9780792373681

Pub. Date: 05/31/2001

Publisher: Springer US

The first edition of Principles of Verifiable RTL Design offered a common sense method for simplifying and unifying assertion specification by creating a set of predefined specification modules that could be instantiated within the designer's RTL. Since the release of the first edition, an entire industry-wide initiative for assertion specification has emerged

Overview

The first edition of Principles of Verifiable RTL Design offered a common sense method for simplifying and unifying assertion specification by creating a set of predefined specification modules that could be instantiated within the designer's RTL. Since the release of the first edition, an entire industry-wide initiative for assertion specification has emerged based on ideas presented in the first edition. This initiative, known as the Open Verification Library Initiative (www.verificationlib.org), provides an assertion interface standard that enables the design engineer to capture many interesting properties of the design and precludes the need to introduce new HDL constructs (i.e., extensions to Verilog are not required). Furthermore, this standard enables the design engineer to 'specify once,' then target the same RTL assertion specification over multiple verification processes, such as traditional simulation, semi-formal and formal verification tools. The Open Verification Library Initiative is an empowering technology that will benefit design and verification engineers while providing unity to the EDA community (e.g., providers of testbench generation tools, traditional simulators, commercial assertion checking support tools, symbolic simulation, and semi-formal and formal verification tools).
The second edition of Principles of Verifiable RTL Design expands the discussion of assertion specification by including a new chapter entitled 'Coverage, Events and Assertions'. All assertions exampled are aligned with the Open Verification Library Initiative proposed standard. Furthermore, the second edition provides expanded discussions on the following topics:

• start-up verification;
• the place for 4-state simulation;
• race conditions;
• RTL-style-synthesizable RTL (unambiguous mapping to gates);
• more 'bad stuff'.
The goal of the second edition is to keep the topic current. Principles of Verifiable RTL Design, A Functional Coding Style Supporting Verification Processes, Second Edition tells you how you can write Verilog to describe chip designs at the RTL level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process.

Product Details

ISBN-13:
9780792373681
Publisher:
Springer US
Publication date:
05/31/2001
Edition description:
2nd ed. 2001
Pages:
282
Product dimensions:
6.14(w) x 9.21(h) x 0.03(d)

Table of Contents

Foreword. Preface. 1. Introduction. 2. The Verification Process. 3. Coverage, Events and Assertions. 4. RTL Methodology Basics. 5. RTL Logic Simulation. 6. RTL Formal Verification. 7. Verifiable RTL Style. 8. The Bad Stuff. 9. Verifiable RTL Tutorial. 10. Principles of Verifiable RTL Design. Bibliography. A. Comparing Verilog Construct Performance. B. Quick Reference. C. Assertion Monitors.

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