Quality-Driven SystemC Design / Edition 1

Quality-Driven SystemC Design / Edition 1

by Daniel Grosse, Rolf Drechsler
     
 

ISBN-10: 904813630X

ISBN-13: 9789048136308

Pub. Date: 12/23/2009

Publisher: Springer Netherlands

A quality-driven design and verification flow for digital systems is developed and presented in Quality-Driven SystemC Design. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction. Second, each verification technique is complemented by an approach to measure

Overview

A quality-driven design and verification flow for digital systems is developed and presented in Quality-Driven SystemC Design. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction. Second, each verification technique is complemented by an approach to measure the achieved verification quality. The new flow distinguishes three levels of abstraction (namely system level, top level and block level) and can be incorporated in existing approaches. After reviewing the preliminary concepts, in the following chapters the three levels for modeling and verification are considered in detail. At each level the verification quality is measured. In summary, following the new design and verification flow a high overall quality results.

Product Details

ISBN-13:
9789048136308
Publisher:
Springer Netherlands
Publication date:
12/23/2009
Edition description:
2010
Pages:
170
Product dimensions:
6.10(w) x 9.30(h) x 0.70(d)

Table of Contents

Dedication. List of Figures. List of Tables. Preface. Acknowledgments.

1. INTRODUCTION.

2. PRELIMINARIES. 2.1 Boolean Reasoning. 2.2 Circuits. 2.3 Formal Verification. 2.4 SystemC.

3. SYSTEM-LEVEL VERIFICATION. 3.1 Constraint-based Simulation. 3.2 Improvements for Constraint-based Simulation. 3.3 Contradiction Analysis for Constraint-based Simulation. 3.4 Measuring the Quality of Testbenches. 3.5 Summary and Future Work.

4. BLOCK-LEVEL VERIFICATION. 4.1 Property Checking. 4.2 Acceleration of Iterative Property Checking. 4.3 Contradictory Antecedent Debugging for Property Checking. 4.4 Analyzing Functional Coverage in Property Checking. 4.5 Summary and Future Work.

5. TOP-LEVEL VERIFICATION. 5.1 Checker Generation. 5.2 HW/SW Co-Verification for Embedded Systems. 5.3 Summary and Future Work.

6. SUMMARY AND CONCLUSIONS.

References. Index.

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