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Rapid Prototyping of Digital Systems provides an exciting and challenging laboratory component for undergraduate digital logic and computer design courses. The more advanced topics and exercises also make this text useful for upper level courses in digital logic or programmable logic. Design engineers working in industry will want to consider this text for a rapid introduction to PPLD technology and logic synthesis using commercial CAD tools.
Rapid Prototyping of Digital Systems includes two tutorials on the Altera CAD tool environment, an overview of programmable logic, and a design library with several easy-to-use input and output functions. These features were developed to help students get started quickly. Early design examples use schematic capture and library components. VHDL is used for more complex designs after a short introduction to VHDL-based synthesis.
The approach used in this text reflects contemporary practice in industry more accurately than the more traditional TTL protoboard-based laboratory courses. Designs containing up to twenty thousand gates are possible with the Altera Student Version CAD tools and the UP 1 board.
Rapid Prototyping of Digital Systems contains a number of interesting and challenging laboratory projects involving serial communications, state machines with video output, video games and graphics, simple computers, keyboard and mouse interfaces, robotics, and a RISC processor core. These projects were all developed on the student version of the Altera CAD tools and can be implemented on the Altera UP 1 board.
1. Tutorial I: The Minute Design. 2. The Altera UP 1 CPLD Board. 3. Programmable Logic Technology. 4. Tutorial II: Sequential Design and Hierarchy. 5. UP1core Library Functions. 6. Using VHDL for Synthesis of Digital Hardware. 7. State Machine Design: The Electric Train Controller. 8. A Simple Computer Design: The muP 1. 9. VGA Video Display Generation. 10. Communications: Interfacing to the PS/2 Keyboard. 11. Communications: Interfacing to the PS/2 Mouse. 12. Robotics: The UP1-bot. 13. A RISC Design: Synthesis of the MIPS Processor Core. Appendix A: Generation of Pseudo Random Binary Sequences Appendix B: MAX+PLUS II Design and Data File Extensions Appendix C: UP I Pin Assignments. Glossary. Index