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It is important to develop and follow a disciplined and optimized design flow when implementing a rapid system prototyping effort. Effective design flow optimization requires addressing the trade-offs between additional project risk and associated schedule reduction. This balance is likely to vary between projects. In order to efficiently implement a project with an optimized design flow system, engineering decisions become even more important since these key decisions affect every subsequent design phase. It is important to understand the design phases, their order, their relationships, and the decisions that must be made in each of these phases. This book attempts to address these topics. Figure 1.1 presents the order of topics addressed within the chapters of this book. This topic order has been arranged to parallel the order of design stages of an FPGA rapid system prototyping effort. Topics that are common to all rapid development FPGA efforts are covered first in the standard topic chapters, while the advanced topic chapters present topics that may not be required in all projects. This book attempts to address commonly avoided topics from a working engineer's perspective, and should promote further discussion and research on important subjects.
The intended audience for this book includes embedded designers with an interest in efficient product development with FPGAs. The text seeks to provide a working introduction to the essential technology fundamentals and common design flows for FPGAs; to provide references to resources for further research on basic and advanced FPGA design topics; and to provide references to resources for FPGA design advanced topics. The order of subjects parallels that of a typical FPGA design flow process.
Each chapter presents an overview of a design topic or phase, provides sources for advanced topic research, and summarizes key concepts with design checklists and concept summaries. Critical design decisions and trade-offs are presented in parallel with common design oversights and applicable design solutions and approaches. The objective is to present the required background knowledge in parallel with practical engineering details, observations, issues, and resolutions. Many design factors are presented in a bulleted list to avoid lengthy text, which can obscure related concepts. The intent is to encourage designers to consider diverse design factors that may impact project development and implementation. Chapter 17 provides an example which brings together all the concepts presented in the book.
Some individuals may enjoy reading academic-style discussions of embedded design topics and then puzzling out how to apply that information to their real-world projects, but this book is not for them. Most engineers like to develop a core understanding of a technology and then jump in and start doing actual design work with minimum delay, and that is the sort of engineer this book has been written for. Following is a breakdown of typical chapter content.
* Present essential engineering background information
* Present design phases and options
* Review concepts, terminology, and acronyms
* Present common design oversights and potential approaches
* Provide sources for further research
Appendix A lists a wide range of manufacturer technical data sources. Appendix B is a collection of checklists which are associated with different stages of FPGA design.
1.1 FPGA rapid Design Implementation potential
Within the digital design field there are three basic types of devices: logic, memory and processors. With recent field programmable gate array (FPGA) architectural evolutions and ever-increasing capacity, it is possible and affordable to implement all three of these elements within FPGA devices. These higher levels of possible design integration continue to expand the range of applications that can be implemented within a single device. FPGAs continue to become more attractive for cost-effective design prototyping based on technology advantages including: design cycle flexibility, reduced-cost design iterations, low "nonrecurring engineering" (NRE) fees, the ability to easily evaluate and implement alternative design architectures, and ability to accelerate time to market for new products.
Today's increasingly rushed projects exhibit a critical need for technology advancements that can accelerate a product's time-to-market. This time to market pressure requires increased system flexibility to hurdle the design issues and changes that inevitably seem to occur. The primary attribute of FPGA technology is flexibility. Flexibility in design implementation and subsequent refinement can lead to significant schedule, complexity and risk reduction. FPGA flexibility can provide the potential for design teams to implement their complex high-performance designs exhibiting a wide range of functionality and interface characteristics quickly and efficiently. Flexibility also allows FPGAs to support efficient design changes and updates with very limited schedule and budget impacts.
FPGAs allow the consolidation of functionality previously requiring multiple integrated circuits into a single device. Figure 1.2 shows an example of a typical system with a traditional discrete implementation of a DSP processor, conventional control processor and FPGA device with external support memory. The latest generations of performance FPGA devices have the potential to implement all of these functions, potentially including the required memory support within a single FPGA device. There are of course many trade-offs to consider regarding this integrated approach, but the technical potential exists to support this implementation. With all of these features implemented within a single device, the flexibility, speed and performance of inter-function communication and interface can be significantly improved. Implementation of traditionally discrete functionality within one or more FPGAs increases the design team's ability to re-architect the functional implementation throughout the life of the project.
1.2 Rapidly Evolving Technology Field
The field of FPGA technology has continued to evolve at a very rapid pace since its earliest days. FPGA vendors have traditionally been locked in battle to improve their product families and increase the volume of parts they deliver to customers. Since most FPGA vendors are "fabless" companies, they can depend on their chip manufacturing foundry partners to efficiently and reliably produce their parts based on the best semiconductor process technology commercially available. This has allowed FPGA vendors to focus on enhancing their device architectures, software tools and intellectual property core offerings.
A constant of the FPGA industry has been a relentless pace of innovation, enhancement and change. These technology advances have been targeted to provide the FPGA designer with increased flexibility and more design implementation options. A result of the constantly increasing FPGA component densities and complexities is the capability to implement increasingly complex designs. FPGA process technologies and architectures continue to advance and evolve. Recent architecture advances include enhanced digital signal processing (DSP) support elements such as dedicated hardware multipliers and larger blocks of embedded and distributed RAM with enhanced features, higher performance embedded processor cores, higher speed input/output (I/O) implementations and expanded FPGA configuration options. These advances serve to expand the range of functionality FPGA components can implement. FPGA tool set improvements have also contributed significantly to a design team's ability to take advantage of FPGA flexibility and features. These broad enhancements are requiring more FPGA designer cross-training within the areas of systems, hardware, software, firmware and DSP engineering.
FPGA vendors are motivated to develop ever-increasing numbers of loyal designers and expand their products into new application spaces. Each FPGA vendor spends significant effort and resources on research, development and design enhancements. While each vendor is focused on differentiating their FPGA families, architectures, software tools and intellectual property offerings from the offerings of their competitors, no "new" feature, architectural enhancement or pricing strategy goes unanswered for long. This competitive market has resulted in numerous "market corrections" as individual FPGA manufacturers have left the market and as technology ownership has been transferred. However, this accelerated pace of innovation has benefited designers and end users alike.
1.3 Design Skill Set Crossover
The field of FPGA design continues to evolve and expand. FPGA technology advancements are driving design teams to gain experience with more design skills than ever before. Today's FPGA engineer may need to be versed in system-level design, functional allocation, embedded processor implementation, DSP algorithm implementation, HDL design entry, simulation, design optimization and high-speed board layout and signal interface. The multiskilled FPGA engineer may require design skills from systems, software and hardware engineering roles. Critical skill areas include basic and advanced FPGA fabric design implementation, embedded processor implementation, implementation of intellectual property (IP) and high-speed board level design.
Few technologies require as broad an experience base as FPGA design to take full advantage of their benefits. FPGA design is a "convergent" technology that requires a complex mix of skills from multiple design specialties. Figure 1.3 represents the engineering role skill overlap between specialties that may be required to implement an advanced FPGA design.
The range of skills required to implement an FPGA project may initially seem overwhelming. For example, even though the design capture and simulation phase of an HDL-based design capture flow is software-intensive, the resulting FPGA device is implemented as a hardware implementation consisting of a mix of I/O elements, memory elements, registers, routing and function-specific circuitry.
Many embedded designers will have skills which are directly applicable to many phases of the FPGA design process. The challenge comes in developing all the skills required to carry a design to completion. Having a multidiscipline design team with a range of specific strengths and experiences is the optimal solution. However, the ideal design team cannot always be assembled due to schedule conflicts and resource limitations. Typical design teams require each member to stretch and develop new skills and capabilities during the course of a project. Ultimately it is desirable for each team member to be familiar with as many elements of the complete FPGA design and development process as possible.
1.4 Hardware Knowledge for Software/Firmware Designers
FPGA technology continues to evolve rapidly in the areas of density, speed, I/O count and interfaces. Taking full advantage of the flexibility of FPGA technology has traditionally required a hardware background or an engineer on the development team with the appropriate hardware experience. Tool and process developments are expanding the group of designers able to take advantage of the FPGA technology potential in new designs.
Many of the concepts and implementation details of FPGA design and development will be familiar to firmware designers due to the development and implementation parallels with embedded firmware design. These parallels are most applicable when the FPGA design process is based on a hardware description language (HDL) design flow. An HDL such as VHDL or Verilog can be used to describe, implement, simulate and test a hardware design implementation within an FPGA. Familiar software design elements resulting from an HDL-based design flow include: levels of abstraction, HDL structures and constructs, iterative design cycles, compiler directives and output file generation, file configuration control, modular design, design reuse, and object-oriented design.
However, even with this common experience base, implementing a hardware design within FPGA components can be a challenge for designers with a primarily software background. There are many details to consider when implementing efficient, reliable hardware function sets within an FPGA with an inherently sequential HDL description language. Many hardware-level decisions must be made and low-level details must be implemented.
Excerpted from Rapid System Prototyping with FPGAs by R.C. Cofer Benjamin F. Harding Copyright © 2006 by Elsevier Inc. . Excerpted by permission of Newnes. All rights reserved. No part of this excerpt may be reproduced or reprinted without permission in writing from the publisher.
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