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This new book by Ben Cohen is an invaluable addition to the existing literature on chip design using the Verilog and VHDL hardware description languages. As Ben notes in his Preface, the purpose of his book is not to teach either HDL, as there are already several books on the market that do an excellent job of describing and teaching the languages. However, as Ben also notes, a sound understanding of the HDL, though a requirement, is not sufficient. Understanding the HDL alone will not make you an expert logic designer, any more than learning C or C++ will make you an expert computer programmer.
One of the things that make this book particularly important is that it doesn't focus on just Verilog or VHDL, but rather on actual design and simulation using examples from both languages. No one actually designs using two languages at the same time, but more and more designers find themselves using IP in a different language or integrating their design with another one written in different language. In addition to driving the need for tools that support both languages, this is also driving the need for designers to understand both Verilog and VHDL at least well enough to be able to debug modules written in either language.
This book concentrates on common classes of hardware architectures and design problems, and focuses on the process of transitioning design requirements into synthesizable HDL code. Using his extensive, wide-ranging experience in computer architecture and hardware design, as well as in his training and consulting work, Ben provides numerous examples of real-life designs illustrated with VHDL and Verilog code. This code is shown in a way that makes it easy for the reader to gain a greater understanding of the languages and how they compare. All code presented in the book is included on the companion CD, along with other information, such as application notes.
Ben also covers a critical aspect for any real-life testbench creation: the use of transaction-based verification techniques. Designs are too complicated to continue to validate them exclusively at the individual signal level. In order to both improve performance and ensure that the tests actually check intended behavior, designers need to create tests and verify results at the transaction level. The book includes a chapter covering on Verilog and VHDL transaction level testing while also referring to C++ based transaction level test tools such as the open-source Testbuilder (available at www.testbuilder.net).
Cadence Design Systems is proud that some of its leading digital verification products were used in the creation of this book. HAL was used for HDL analysis and lint checking, which provides a perfect static verification complement to the dynamic simulation featured in the rest of the book. The high-performance, mixed-language simulator NC-Sim was used for verifying all of the examples in the book and the results were shown using the SimVision GUI and debug environment.
This book is one of the best investments that a logic designer can make. We are certain that it will be of enormous value to all those involved in HDL-based chip design for years to come.
Corporate Vice President - Systems and Functional Verification.
Cadence Design Systems, Inc.