As the complexity of on-chip integrated systems continues to increase, designing high-performance mixed-signal system becomes increasingly challenging. One major obstacle with design and synthesis of such systems in practice is the lack of a fast, accurate way to evaluate the system performance. The problem becomes more pressing as the IC feature size scales to the sub-100nm regime, and the relative increases in process variations bring more uncertainties to the circuit performance. To expedite design analysis, response surface models are commonly used to represent the circuit or system performance by abstracting the internal circuit details. In this thesis we propose a novel methodology to build response surface models that capture a large parameter space. The proposed modeling framework is facilitated by a novel piecewise approximation algorithm that recursively partitions the large parameter space into small local ones. Importantly, the high-dimensional space partition problem is formulated as a convex optimization that can be reliably solved to find the optimal partitioning. The dissertation will demonstrate two major applications of the proposed response surface modeling framework in the design space and in the variation space respectively. First, a method for creating parameterized analog macromodels is proposed where the coefficient matrices in the system equation are captured as piecewise response surface models with design variables as parameters. Such macromodels are intended for design exploration. A multi-point parameterized model order reduction technique is developed to effectively compress the piecewise macromodel. Our experiments demonstrate that using the obtained macromodels can achieve more than 60x speed-up while incurring less than 4% overall error as design parameters vary by an order of magnitude. Second, SRAM cell stability metrics are modeled utilizing the proposed framework to cover the large process variation range demanded by the extremely high yield requirement. We then propose a controlled sampling scheme and a nested Monte Carlo analysis method respectively for the failure probability extraction at the cell-level and at the chip-level. Our 65nm SRAM design example shows that the proposed model and analysis method combine to offer runtime reduction of 105x to 108x as compared with simulation based Monte Carlo analysis.