Robustness and Usability in Modern Design Flows / Edition 1by Gorschwin Fey, Rolf Drechsler
Pub. Date: 01/11/2008
Publisher: Springer Netherlands
The size of technically producible integrated circuits increases continuously. But the ability to design and verify these circuits does not keep up with this development. Therefore today’s design flow has to be improved to achieve a higher productivity. In Robustness and Usability in Modern Design Flows the current design methodology and verification… See more details below
The size of technically producible integrated circuits increases continuously. But the ability to design and verify these circuits does not keep up with this development. Therefore today’s design flow has to be improved to achieve a higher productivity. In Robustness and Usability in Modern Design Flows the current design methodology and verification methodology are analyzed, a number of deficiencies are identified and solutions suggested. Improvements in the methodology as well as in the underlying algorithms are proposed.
An in-depth presentation of preliminary concepts makes the book self-contained. Based on this foundation major design problems are targeted. In particular, a complete tool flow for Synthesis for Testability of SystemC descriptions is presented. The resulting circuits are completely testable and test pattern generation in polynomial time is possible. Verification issues are covered in even more detail. A whole new paradigm for formal design verification is suggested. This is based upon design understanding, the automatic generation of properties and powerful tool support for debugging failures. All these new techniques are empirically evaluated and experimental results are provided.
As a result, an enhanced design flow is created that provides more automation (i.e. better usability) and reduces the probability of introducing conceptual errors (i.e. higher robustness).
- Springer Netherlands
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- 9.21(w) x 6.14(h) x 0.50(d)
Table of Contents
Dedication. List of Figures. List of Tables. Preface.
2. Preliminaries. 2.1 Boolean Reasoning. 2.2 Circuits. 2.3 Formal Verification. 2.4 Automatic Test Pattern Generation.
3. Algorithms and Data Structures. 3.1 Combining SAT and BDD Provers. 3.2 Summary and Future Work.
4. Synthesis. 4.1 Synthesis of SystemC. 4.2 Synthesis for Testability. 4.3 Summary and Future Work.
5. Property Generation. 5.1 Detecting Gaps in Testbenches. 5.2 Design Understanding. 5.3 Summary and Future Work.
6. Diagnosis. 6.1 Comparing SAT-based and Simulation-based Approaches. 6.2 Generating Counterexamples for Diagnosis. 6.3 Debugging Properties. 6.4 Summary and Future Work.
7. Summary and Conclusions.
References. Index of Symbols. Index.
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