Silicon Processing for the VLSI Era: Deep-Submicron Process Technology

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Editorial Reviews

From The Critics
This final volume in a set dedicated to advances in semiconductor technologies focuses exclusively on techniques needed to manufacture chips for 0.18-micron generations. Among the process technologies described are copper/low-k dual-damascene interconnects; high- k MOSFET-gate and DRAM dielectrics; 300-mm wafers; chemically- mechanical polishing; excimer-laser-based DUV lithography; chemically- amplified resists; silicon:germanium (Si:Ge); and silicon-on- insulator. Annotation c. Book News, Inc., Portland, OR
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Product Details

  • ISBN-13: 9780961672171
  • Publisher: Lattice Press
  • Publication date: 5/28/2002
  • Edition description: New Edition
  • Pages: 806

Table of Contents

Chap. 1 The Evolution of the Structure of Mosfets 1
Chap. 2 300-MM Silicon Wafers 17
Chap. 3 Gate Dielectrics: Thin Gate Oxides 75
Chap. 4 High-k Dielectrics 145
Chap. 5 The Structure of Deep-Submicron Mosfets: Retrograde-Wells; Super-Steep Retrograde Channel Doping; Drain Engineering; Punchthrough-Control Implants 181
Chap. 6 Deep-Submicron Lithography I: Photoresists 227
Chap. 7 Deep-Submicron Lithography II: Optics and Hardware 259
Chap. 8 Chemical Mechanical Polishing (Cmp) 313
Chap. 9 Shallow Trench Isolation (Sti) 433
Chap. 10 Silicon-Germanium (Si-Ge) Technology for High-Performance Telecommunications ICs 475
Chap. 11 Silicon-On-Insulator (Soi) Technology 501
Chap. 12 Multilevel Interconnects for Ulsi 573
Chap. 13 Polycides and Salicides of Tisi[subscript 2], CoSi[subscript 2] and NiSi 603
Chap. 14 Low-k Dielectrics 639
Chap. 15 Dual-Damascene Interconnects 671
Chap. 16 Copper Interconnect Process Technology 711
Index 795
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