Silicon Processing for the VLSI Era: Process Integration

Silicon Processing for the VLSI Era: Process Integration

by Stanley Wolf, Richard N. Tauber
     
 

ISBN-10: 0961672145

ISBN-13: 9780961672140

Pub. Date: 03/01/1990

Publisher: Lattice Press

Silicon Processing For The VLSI Era is a 3 volume treatise which provides a comprehensive, up-to-date treatment of this technology. Volume 1 covers the details of individual process steps used in fabricating silicon ICs. Volume 2 describes how these process steps are combined to make VLSI and ULSI structures. Volume 3 discusses the physics of MOS devices,…  See more details below

Overview

Silicon Processing For The VLSI Era is a 3 volume treatise which provides a comprehensive, up-to-date treatment of this technology. Volume 1 covers the details of individual process steps used in fabricating silicon ICs. Volume 2 describes how these process steps are combined to make VLSI and ULSI structures. Volume 3 discusses the physics of MOS devices, emphasizing the link between submicron MOSFETs and their manufacturing processes. The books are an outgrowth of a set of intensive seminars conducted through the University of California Berkeley, Engineering Extension, for the past fifteen years. Over four thousand engineers and managers from more than 75 companies and government agencies have taken these courses since they were first presented in 1984.

Product Details

ISBN-13:
9780961672140
Publisher:
Lattice Press
Publication date:
03/01/1990
Edition description:
New Edition
Pages:
753

Table of Contents

Preface

Chap. 1 - Process Integration for VLSI and ULSI ..... 1

1.1 Process Integration ..... 5
1.1.1 Process Sequence Used to Fabricate an Integrated-Circuit MOS Capacitor ..... 5
1.1.2 Specifying a Process Sequence ..... 6
1.1.3 Levels of Process Integration Tasks ..... 7
1.2 Process-Development and Process-Integration Issues ..... 8
References ..... 11

Chap. 2 - Isolation Technologies for Integrated Circuits ..... 12

2.1 Basic Isolation Processes for Bipolar ICs ..... 13
2.1.1 Junction Isolation ..... 13
2.1.1.1 Junction Isolation in the SBC Process
2.1.1.2 Collector-Diffusion Isolation
2.2 Basic Isolation Process for MOS ICs (LOCOS Isolation) ..... 17
2.2.1 Punchthrough Prevention between Adjacent Devices in MOS Circuits ..... 20
2.2.2 Details of the Semirecessed Oxide LOCOS Process ..... 20
2.2.2.1 Pad-Oxide Layer
2.2.2.2 CVD of Silicon Nitride Layer
2.2.2.3 Mask and Etch Paf-Oxide/Nitride Layer to Define Active Regions
2.2.2.4 Channel-Stop Implant
2.2.2.5 Problems Arising from the Channel-Stop Implants
2.2.2.6 Grow Field Oxide
2.2.2.7 Strip the Masking Nitride/Pad-Oxide Layer
2.2.2.8 Regrow Sacrificial Pad Oxide and Strip (Kooi Effect)
2.2.3 Limitations of Conventional Semi-Recesses Oxide LOCOS for Small-Geometry ICs ..... 27
2.3 Fully Recessed Oxide LOCOS Processes ..... 28
2.3.1 Modeling the LOCOS Process ..... 31
2.4 Advanced Semirecesses Oxide LOCOS Isolation Processes ..... 31
2.4.1 Etched-Back LOCOS ..... 31
2.4.2 Polybuffered LOCOS ..... 32
2.4.3 SILO(Sealed-Interface Local Oxidation) ..... 33
2.4.4 Laterally Sealed LOCOS Isolation ..... 35
2.4.5 Bird's Beak Suppression in LOCOS by Mask-Stack Engineering ..... 38
2.4.6 Planarized SILO with High-Energy Channel-Stop Implant ..... 38
2.5 Advanced Fully Recessed Oxide LOCOS Isolation Processes ..... 39
2.5.1 SWAMI (Sidewall-Masked Isolation Technique) ..... 39
2.5.2 SPOT (Self-Aligned Planar-Oxidation Technology) ..... 41
2.5.3 FUROX (Fully Recessed Oxide) ..... 41
2.5.4 OSELO II ..... 43
2.6 Non-LOCOS Isolation Technologies I: (Trench Etch and Refill) ..... 45
2.6.1 Shallow Trench and Refill Isolation ..... 45
2.6.1.1 BOX Isolation
2.6.1.2 Modifications to Improve BOX Isolation
2.6.2 Moderate-Depth Trench and Refill Isolation ..... 48
2.6.2.1 U-Groove Isolation
2.6.2.2 Toshiba Moderate-Depth Trench Isolation for CMOS
2.6.3 Deep, Narrow Trench and Refill ..... 51
2.6.3.1 Reactive Ion Etching of the Substrate
2.6.3.2 Refilling the Trench
2.6.3.3 Planarization after Refill
2.7 Non-LOCOS Isolation Technologies, II: Selective Epitaxial Growth (SEG) ..... 58
2.7.1 Refill by SEG of Windows Cut into Surface Oxide ..... 59
2.7.2 Simultaneous Single-Crystal/Poly Deposition (SSPD) ..... 60
2.7.3 Etching of Silicon Trenches and Refilling with SEG to Form Active Device Regions ..... 61
2.7.4 Selective-Epitaxial-Layer Field Oxidation (SELFOX) ..... 61
2.7.5 SEG Refill of Trenches (as an Alternative to Poly Refill) ..... 62
2.7.6 Epitaxial Lateral Overgrowth (ELO) ..... 62
2.8 Miscellaneous Non-LOCOS Isolation Technologies ..... 63
2.8.1 Field-Shield Isolation
2.8.2 Buried Insulator between Source/Drain Polysilicon (BIPS) ..... 64
2.9 Summary: Candidate Isolation Technologies for Submicron Devices ..... 65
2.9.1 Basic Requirements of VLSI and ULSI Isolation Technologies ..... 65
2.9.2 The Need for Planarity ..... 65
2.9.3 How the Various Isolation Technologies Meet the Requirements ..... 66
2.10 Silicon-On-Insulator (SOI) Isolation Technologies ..... 66
2.10.1 Dielectric Isolation
2.10.2 Wafer Bonding
2.10.3 Silicon-on-Sapphire (SOS)
2.10.4 Separation by Implanted Oxygen (SIMOX) ..... 72
2.10.5 Zone-Melting Recrystallization (ZM

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