SOI Circuit Design Concepts / Edition 1

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Overview

This book first introduces SOI device physics and its fundamental idiosyncrasies. It then walks the reader through realizations of these mechanisms, which are observed in common high-speed microprocessor designs. The book also offers rules of thumb and comparisons to conventional bulk CMOS to guide implementation and describes a number of unique circuit topologies that SOI supports.

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Product Details

  • ISBN-13: 9780792377627
  • Publisher: Springer US
  • Publication date: 1/1/2000
  • Edition description: 2000
  • Edition number: 1
  • Pages: 222
  • Product dimensions: 0.63 (w) x 6.14 (h) x 9.21 (d)

Read an Excerpt


Chapter 1: The Time for SOI

1.1 Technology Scaling in VLSI

Very Large Scale Integration (VLSI) employing bulk-substrate CMOS technology is truly the industrial success story of the twentieth century. In a relatively brief period of time, CMOS has not only replaced bipolar transistors in most commercial applications, it has defined whole new markets and applications. The engine behind this phenomena, Technology Scaling, has fueled relentless growth in semiconductor performance and density.

Scaling refers to an observation made by Bob Dennard, et al, in 1974 that the features of an idealized transistor and interconnect, when migrated from one technology generation to the next, may all be translated by a common scaling factor [ 1.1 ]. Observing this scale factor then maintains established optimum electrical properties.

Rule of thumb: Historically, scaling factors of 1.25 to 1.33 have been realized in moving to next-generation technologies.

Figure 1.1 depicts a number of these physical device parameters in a common N-type MOSFET in a "common substrate"], and their relationship to scaling factor a. In an idealized setting, scaling to the next generation technology has enabled density, performance, and power to improve by a factor of a2, a, and (I/a2), respectively.

As a result, CMOS processor performance has been increasing at a rate predicted by Moore's Law, 2X every 18 months. Figure 1.2 graphically displays this story over the past 20 years. Product designers leveraged this improved performance and density by integrating function previously done in separate components on board the processor. Because of this, die size and chip power have not been decreasing rapidly.

1.2 The End of Moore's Law?

Time has taken its toll on Moore's law. Figure 1.3 shows the original fit to design points from the seventies [1.2] and a return by its progenitor to the observation in 1995 [1.3]. The reduced gain per generation is attributed to a number of factors associated with increased complexity. The departure from this idealized fit is observed to be getting worse. A more profound limitation, capable of dramatically impacting Moore's Law and scaling, has emerged more recently, however, and is the motivation for the development of SOI technology. So please read on!

The predominant boundary to scaling was determined by limitations found in the fabrication tools (i.e. minimum feature size phtolithography) and materials of the current technology (i.e gate dielectrics). It is now becoming apparent that MOSFET device threshold voltages may no longer be reduced much more, due to

(a) excessive subthreshold leakage impacting circuit function,

(b) precarious noise immunity,

(c) non-conducting device wearout limitations, and

(d) chip standby power.

To counter the resulting net loss of overdrive by not reducing threshold voltage, VDD in turn has not been reduced by the full scaling factor. As physical dimensions of the device have continued to scale, however, the growing lateral electric field in the MOSFET has degraded device mobilities and hence the performance gain per generation, as shown in Figure 1.4 [1.4].

Given this limitation to threshold voltage reduction, it is obvious that in the absence of the introduction of new technologies, CMOS performance will continue to flatten or may actually degrade. Figure 1.5 shows actual inverter delays reported in the literature plotted with a prediction of future bulk CMOS performance [1.5]. Various predictions have anticipated the useful lifetime of the present CMOS device technology paradigm. Credible arguments anticipate performance improvements are severely curtailed by the 100 nm lithography generation [1.5]. The resulting erosion of performance in the microprocessor would soon become quite pronounced, in lieu of a device alteration. Figure 1.6 shows expected trends in microprocessor cycle time in the not-too-distant future.[1.6]

Students of VLSI may argue that soothsayers have been predicting the end of Moore's Law every year since its inception; while somehow the industry has continued to find solutions, the coming generation's challenges are more ominous.

Works in the literature have proposed technologies deliberately accepting high leakage. It has been shown that CMOS may be operated very efficiently when a transistor's ION is equal to 'OFF, occurring at approximately 400 mV [1.7]. This novel approach to logic computation requires an infrastructure and a paradigm change which industry has not yet displayed a willingness to accept.

With the chip designer being forced to accept painful characteristics to continue improving performance conventionally, it was clear that new transistor technologies would be needed, as VDD approaches 1.0 V, in order to continue. Unlike the transition from bipolar to CMOS transistors, no fundamentally different semiconductor device is waiting in the wings to replace CMOS. It follows, then, that alterations which enhance the field-effect transistor's transconductance while leveraging existing design tools and methodologies would be of great interest. SOI technology matches this description quite nicely.

1.3 The Case for PD- SOI

1.3.1 Why Partially Depleted SOI?

The motivation for moving to SO[ clearly is to extend scalability of CMOS, to continue enjoying performance as well as density benefits of migrating designs and architectures to next generation lithographies. It makes sense then, that the following would be first order considerations in selecting a transistor device technology:

1. Process Commonality
PD-SOI may be thought of as a evolutionary rather than revolutionary device structure, in that with the exception of the wafer SIMOX formation, the CMOS wafer fabrication is performed on the same bulk CMOS tool set, targeting parameters which are either similar or identical to bulk CMOS.

2. Scalability
A device definition which, when scaled through successive lithographies, continues to produce a viable product is very important. Because PD-SOI does not require the ultra-thin active silicon thicknesses typically used in fully-depleted (FD) SOI, investments in its developed can be returned over more generations

3. Tolerance
Using identical materials, tools, processes, and parameter targets as in its bulk predecessor, the spatial variability in SOI electrical parameters is well established and accommodated in the software tools commonly used. That leaves the use dependent variation, which can be shown to be well modeled.

With FD-SOI, the entire body of the transistor is inverted. The threshold voltage, therefore, is a function of the charge contained in the body, and can vary substantially across chip. As active silicon thickness is driven thinner, this becomes a boundary condition [ 1.8]. The reader is referred to the literature for more details on FD-SOI [ 1.9].

4. Few emerging alternatives exist
CMOs LSI was developed as bipolar technologies were being used in most high speed applications. When CMOs matured enough to be viable based on performance, power and cost, the transition was made. Unlike those times, there is no new paradigm in transistor electronics waiting "in the wings." Until an entirely new successor is established, our industry will continue to introduce innovative CMOs variations such as SOI into volume production...

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Table of Contents

Preface. 1: The Time for SOI. 1.1. Technology Scaling in VLSI. 1.2. The End of Moore's Law? 1.3. The Case for PD-SOI. 1.4. Summary. 2: SOI Device Structures. 2.1. Introduction. 2.2. Wafer Fabrication. 2.3. Patterning SOI Regions. 2.4. Transistor Structures. 2.5. Diodes. 2.6. Resistors. 2.7. Decoupling Capacitors. 2.8. Summary. 3: SOI Device Electrical Properties. 3.1. Introduction. 3.2. SOI MOSFET's Junction Diode. 3.3. Impact Ionization. 3.4. Floating Body Effects. 3.5. SOI MOSFET Modeling. 3.6. Insulator-Related Effects. 3.7. Composite Responses. 3.8. Summary. 4: Static Circuit Design Response. 4.1. Introduction. 4.2. Parameters of Interest to Circuit Designers. 4.3. First Switch vs. Second Switch. 4.4. First Switch vs. Steady State. 4.5. Static Circuit Response to SOI. 4.6. Passgate Circuit Response. 4.7. Summary. 5: Dynamic Circuit Design Considerations. 5.1. Introduction. 5.2. Dynamic Circuit Response. 5.3. Preferred Dynamic Design Practices. 5.4. Keeping Dynamic SOI Problems in Perspective. 5.5. Soft Errors in Dynamic Logic. 5.6. Dynamic Logic Performance. 5.7. Conclusions. 6: SRAM Cache Design Considerations. 6.1. Overview. 6.2. Writing a Cell. 6.3. Reading a Cell. 6.4. Cell Stability and Cell Bias. 6.5. SRAM Noise Considerations. 6.6. Precharging Circuitry. 6.7. Soft Error Upsets. 6.8. Array Test in PD-SOI. 6.9. Summary. 7: Specialized Function Circuits in SOI. 7.1. Introduction. 7.2. Timing Elements. 7.3. Latch Response in SOI. 7.4. Input/Output Circuitry. 7.5. Electro-Static Discharge (ESD) Protection. 7.6. Summary. 8: Global Chip Design Considerations. 8.1. Introduction. 8.2. Temperature Effects. 8.3. Noise Immunity. 8.4. Power Consumption. 8.5. Power Supply Issues Noise. 8.6. System Performance. 8.7. SOI Timing Variability. 8.8. Summary. 9: Future Opportunities in SOI. 9.1. Introduction. 9.2. Floating body Effect Suppression. 9.3. DTCMOS. 9.4. DGCMOS. 9.5. 3-Dimensional SOI. 9.6. Future Scaling Opportunities. 9.7. Summary. About the Authors. Index.

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