Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms

Overview

One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a shastic process. In addition to wide-sense...

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Overview

One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a shastic process. In addition to wide-sense stationary shastic device variability and temperature variation, existence of non-stationary shastic electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits.

In an attempt to address these issues, Shastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms offers unique combination of mathematical treatment of random process variation, electrical noise and temperature and necessary circuit realizations for on-chip monitoring and performance calibration. The associated problems are addressed at various abstraction levels, i.e. circuit level, architecture level and system level. It therefore provides a broad view on the various solutions that have to be used and their possible combination in very effective complementary techniques for both analog/mixed-signal and digital circuits. The feasibility of the described algorithms and built-in circuitry has been verified by measurements from the silicon prototypes fabricated in standard 90 nm and 65 nm CMOS technology.

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Product Details

  • ISBN-13: 9789400777804
  • Publisher: Springer Netherlands
  • Publication date: 12/31/2013
  • Series: Springer Series in Advanced Microelectronics , #48
  • Edition description: 2014
  • Pages: 192
  • Product dimensions: 6.14 (w) x 9.21 (h) x 0.50 (d)

Meet the Author

Amir Zjajo received the M.Sc. and DIC degrees from the Imperial College London, London, U.K., in 2000 and the Ph.D. degree from Eindhoven University of Technology, Eindhoven, The Netherlands in 2010, all in electrical engineering. In 2000, he joined Philips Research Laboratories as a member of the research staff in the Mixed-Signal Circuits and Systems Group. From 2006 until 2009, he was with Corporate Research of NXP Semiconductors as a senior research scientist. In 2009, he joined Delft University of Technology as a Faculty member in the Circuit and Systems Group.

Dr. Zjajo has published more than 70 papers in referenced journals and conference proceedings, and holds more than 10 US patents or patents pending. He is the author of the book Low-Voltage High-Resolution A/D Converters: Design, Test and Calibration (Springer, 2011, Chinese translation, 2012). He serves as a member of Technical Program Committee of IEEE Design, Automation and Test in Europe Conference, IEEE International Symposium on Circuits and Systems and IEEE International Mixed-Signal Circuits, Sensors and Systems Workshop. His research interests include mixed-signal circuit design, signal integrity and timing and yield optimization.

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Table of Contents

1 Introduction.
1.1 Shastic Process Variations in Deep-Submicron CMOS. 1.2 Remarks on Current Design Practice. 1.3Motivation. 1.4 Organization of the Book.

2. Random Process Variation in Deep-Submicron CMOS.
2.1 Modeling Process Variability. 2.2 Shastic MNA for Process Variability Analysis. 2.3 Statistical Timing Analysis. 2.4 Yield Constrained Energy Optimization. 2.5 Experimental Results. 2.6 Conclusions.

3 Electronic Noise in Deep-Submicron CMOS.
3.1 Shastic MNA for Noise Analysis. 3.2 Accuracy Considerations. 3.3 Adaptive Numerical Integration Methods. 3.4 Estimation of the Noise Content Contribution. 3.5 Experimental Results. 3.6 Conclusions.

4 Thermal Effects in Deep-Submicron CMOS.
4.1 Thermal Model. 4.2 Temperature Estimation. 4.3 Reducing Computation Complexity. 4.4 System Level Methodology for Temperature Constrained Power Management. 4.5 Experimental Results. 4.6 Conclusions.

5 Circuit Solutions.
5.1 Architecture of the System. 5.2 Circuits for Active Monitoring of Temperature and Process Variations. 5.3 Characterization of Process Variability Conditions. 5.4 Experimental Results. 5.5 Conclusions.

6 Conclusions and Recommendations.
6.1 Summary of the Results. 6.2 Recommendations and Future Research.

Appendix. References. Acknowledgement. About the Author.

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