Symbolic Simulation Methods for Industrial Formal Verification / Edition 1

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This volume contains two distinct, but related, approaches to the verification problem, both based on symbolic simulation. It describes new ideas that enable the use of formal methods, specifically symbolic simulation, in validating commercial hardware designs of remarkable complexity.

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Editorial Reviews

From The Critics
As the problem of buggy computer hardware increases faster than other innovations of design, the solution has been to beef up conventional approaches to formal verification, which entails exhaustive analysis of some aspect of design behavior. Jones, an electrical engineer at Intel, suggests symbolic simulation as a highly effective and somewhat neglected alternative. He admits that the approach does have computational limits, but says they are not as severe in practice as formal verification, and can be used so that performance degrades gracefully rather than hitting hard limits. He emphasizes new ways to use symbolic simulation to verify and debug complex hardware systems. Annotation c. Book News, Inc., Portland, OR
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Product Details

  • ISBN-13: 9781402071034
  • Publisher: Springer US
  • Publication date: 6/30/2002
  • Edition description: 2002
  • Edition number: 1
  • Pages: 151
  • Product dimensions: 0.44 (w) x 6.14 (h) x 9.21 (d)

Table of Contents

List of Figures
List of Tables
1 Introduction 1
1.1 Motivation and Philosophy 1
1.2 Approach 3
1.3 Verification Realities 4
1.4 Introduction to Symbolic Simulation 5
1.5 Other Approaches 11
1.6 Scope of the Book 13
1.7 Outline 15
2 Self Consistency 19
2.1 Computer Architecture Concepts and Terms 19
2.2 Introduction to Self Consistency 22
2.3 Definitions 25
2.4 Pragmatics 26
2.5 Verification Reduction 27
2.6 Examples 29
2.7 Related Work 32
3 Self Consistency in Practice 35
3.1 Overview 35
3.2 P6 Retirement Pipeline 38
3.3 IA-32 Instruction-Length Decoder 44
4 The Parametric Representation 55
4.1 Introduction 55
4.2 Verification Decomposition 57
4.3 Computation and Correctness 60
4.4 Input-Space Partitioning 64
4.5 Integration with STE and Theorem Proving 67
4.6 Related Work 68
5 Using the Parametric Representation 73
5.1 Overview of Examples 73
5.2 Instruction-Length Decoder (IM) 75
5.3 Floating-Point Addition and Subtraction 87
6 Background on Processor Verification 97
6.1 Introduction 97
6.2 Burch/Dill Flushing 98
6.3 The Logic and Validity Checking 100
6.4 The Stanford Validity Checker 102
6.5 Related Verification Examples 103
7 Incremental Flushing 105
7.1 Introduction 106
7.2 Preliminaries 107
7.3 The Approach 109
7.4 M[subscript 1] Flush-Point Simulates M[subscript A] 110
7.5 M[subscript A] Flush-Point Simulates M[subscript s] 112
7.6 Mechanical Verification 119
7.7 Related Work 119
8 Conclusions 125
Appendices 127
Proofs 127
A.1 Proof of Theorem 3 127
A.2 Proof of Theorem 5 131
A.3 Statement and Proof of Lemma 1 132
A.4 Proof of Theorem 8 133
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