## Read an Excerpt

#### Synchronous Precharge Logic

**By Marek Smoszna**

**Elsevier Science**

**Copyright © 2012 Elsevier Inc.**

All rights reserved.

ISBN: 978-0-12-401707-8

All rights reserved.

ISBN: 978-0-12-401707-8

#### Excerpt

#### CHAPTER 1

**Precharge Logic Basics**

**1.1 Introduction**

The purpose of this book is to describe the issues involved in precharge circuit design and to establish design guidelines that will minimize the design risk. Anyone designing dynamic circuits or full swing memories should read this book.

There are many logic families utilizing the metal oxide semiconductor (MOS) transistor. Static complementary metal oxide semiconductor (CMOS) is the most widely used, partly because it is safe. "Safe" means that it will almost always work without any special considerations. However, sometimes static logic just is not good enough. In advanced very large scale integration (VLSI) systems such as microprocessors, there arise "critical" logic paths where static logic is just too slow to meet the timing constraints. There are faster logic families, and precharge (dynamic) logic is one of them. Precharge logic also has other advantages over static logic. Of course, there are also disadvantages, and design with precharge logic is more challenging to ensure proper circuit operation.

This book covers synchronous (clocked) precharge logic. "Clocked" simply means that the clock is used to (indirectly) precharge the outputs of the logic gates. There exists also asynchronous precharge logic, but the clocked version is simpler and more popular. This type of logic is widely called "dynamic" logic in the industry, where "dynamic" simply means relying on charge storage, and "static" means "always driven." But because "keepers" can be added to the dynamic nodes, this type of logic can be dynamic or static. Thus, "precharge logic" appears to be a more appropriate name. Keepers will be explained in detail in **Section 1.7** and in Chapter 3.

**1.2 What Is Precharge Logic?**

A basic precharged NAND gate is shown in **Figure 1.1**. The logic gate consists of an N-channel metal oxide semiconductor (NMOS) tree of transistors known as the "pulldown stack." The output is precharged HIGH by the P-channel metal oxide semiconductor (PMOS) device when the clock is LOW. The output is conditionally discharged when the clock turns on the NMOS device connected to ground. This is known as the evaluation device or "footer." Discharge of the output happens when the clock is HIGH and the inputs create a path in the NMOS tree from the output node to the bottom NMOS device. The clock can be replaced with a signal named "/precharge," as in the general case the precharge/evaluate functions can be controlled with any signal. An example would be an asynchronous system where there are no clocks. In any case, please note that we precharge HIGH and evaluate LOW because of the good efficiency of the NMOS devices. Predischarging LOW and evaluating HIGH would not be as efficient.

Some common terms used are as follows (**Figure 1.2**):

the *precharge phase* is when the clock input to a circuit is low, the *evaluation phase* is when the clock input to a circuit is high.

**1.3 Why Is it Faster than Static Logic?**

Precharge logic gets its speed from the fact that the pullup tree (single P-channel field effect transistor (PFET)) and the pulldown tree are never on at the same time. When a static gate switches, there is an overlap time when the two trees are "fighting." Precharge logic separates the pullup and pulldown times, as can be seen in **Figure 1.3**. If we want to discharge the output (pull it down), then the only current flowing in the NMOS tree is from the charge stored on the output node. In static logic, there is also a short circuit (crowbar) current that flows from *V*_{dd} to *V*_{ss}, and so the peak transition current in static logic is higher than in precharge logic. Because the crowbar current exists directly between *V*_{dd} and *V*_{ss}, it can be seen that this current does no logical work and is therefore wasted power. More importantly, as the current in the metal oxide semiconductor field effect transistor (MOSFET) is not solely from the charge stored in the load capacitance, it takes longer to discharge the load in static logic.

Another factor in the precharge logic speedup is the fact that the dynamic node starts to pull down when the input reaches the transistor threshold voltage *V*_{t}. This is sooner than in the static gate, which begins switching when the input reaches roughly *V*_{dd}/2.

So the pulldown speed is improved considerably, even though there is typically an extra NMOS device in series with the NMOS logic tree. This is of course the clock-controlled footer, connected to *V*_{ss}. The pullup time experiences the biggest improvement in speed because there is only one pullup device (as opposed to a series P stack). But because this is the precharge time, it is typically not critical and so timing can be adjusted depending on how one sizes the device.

One may ask how this logic can be faster if a whole half of a clock cycle is dedicated to precharging the output. The answer is that the whole picture must be considered, meaning the logic and latches/registers separating the logic stages. In a typical two-phase clocking scheme, each logic stage is only given one half of a clock cycle to evaluate anyway. So while one block is evaluating, another is precharging and vice versa, as can be seen in **Figure 1.4**.

There are other ways of using precharge logic, as described in Ref. [3]. In this case, static and precharge logics are interleaved and static logic propagates signals while precharge logic is being precharged. In this way, there is still signal propagation on every phase. This approach is a compromise between using static and precharge logics.

There are times when precharge logic is not faster than static. With latch-based clocking schemes, static logic can take advantage of "time borrowing", which may result in better timing than precharge logic. Time borrowing simply means that signals can flow to the next block of logic without having to wait for a clock edge. Thus, the next block starts evaluating early, in a way "borrowing" time from the current block. But precharge gates can sometimes take advantage of time borrowing. If the logic stages on both sides of a latch consist of precharge logic, then time borrowing is possible. This is done by overlapping the evaluation phases of both stages. We will discuss this in detail in Chapter 2. Furthermore, the use of a dual monotonic (dual rail, precharged) latch also removes the synchronization point that is created between latches and precharge logic blocks. It is therefore clear that there are numerous ways to overcome synchronization point problems in precharge logic. As with other logic families, a logic chain is limited by the duration of the evaluation phase. All outputs must be stored at the point that the latch on the output closes.

Let us now summarize the factors that impact the speed of precharge logic:

• no fighting between PMOS and NMOS trees,

• evaluation starts as soon as we reach [V.sub.tn] of the NMOS device,

• lower input capacitance for the same output current,

• inverting static gate can be skewed in favor of the critical edge.

**1.4 Advantages of Precharge Logic**

There are a number of advantages to using precharge logic. As mentioned above, precharge logic is faster than static logic due to several factors. In addition, the precharge logic gates are smaller in physical size because there is only a single PMOS pullup device. Of course, this only holds true when implementing Boolean functions that are more complicated than a simple inverter. Not having to implement a full PMOS tree can thus result in large savings in areas in logic gates with a large fan. The reason for this is that the carrier mobility in PMOS devices is lower than that of NMOS devices. This condition requires the use of significantly larger PMOS devices to achieve the same resulting conductivity as that of the smaller NMOS devices. In addition to the area penalty for the larger PMOS devices, a performance penalty will be paid for their use due to self-loading and input loading. Self-loading comes from the fact that any increase in the node capacitance on the output of a logic gate will reduce its performance. So as we increase the width of a transistor, its associated parasitic capacitance increases as well. The reduction to self-loading (as compared to static circuits) allows the efficient construction of gates such as an 8 input multiplexer or NOR gate.

Because the precharge logic gates are smaller, the gates that drive them can also be smaller. Naturally, this is because the precharged gates present a smaller load capacitance to their drivers. The other way to look at this is that the driving gates can be faster, if not reduced in size. Not reducing the driver size may not be the best choice; however, a fanout of 3 to 4 is known to be optimum for most applications. Furthermore, larger gates may still not be able to compensate for wire RC, as shown in **Figure 1.5**. If there are two resistors in series, the total resistance can never be smaller than any one of the resistors.

So far it was established that precharged gates are faster because there is no fighting between the pullup and pulldown networks. It also was pointed out that the pulldown time is not improved as much as the pullup time because there is still a full NMOS tree of transistors and there is an additional NMOS device placed in series with the tree. But as we will learn in **Section 1.6**, just about all precharged gates are followed by a static inverter, as shown in **Figure 1.6**, which happens to be a NOR gate. While this will be discussed in detail in **Section 1.6**, it is worth pointing out that with the static inverter, the whole logic gate can evaluate faster, even with the additional propagation delay from the inverter. This is due to the fact that now there are not any series transistor stacks driving the next gate, there is only an inverter with a single PMOS and NMOS device, driving the load with an inverter is potentially the fastest one can get in a given technology. In order for the inverter to provide such improvement in speed, its PMOS device should be sized much larger than its NMOS device. However, this severely reduces the noise margin. In fact, some people increase the NMOS device to improve the noise margin at the expense of speed. If a circuit is designed to be fast but it does not work on actual silicon, then it is useless. Improvements to the noise margin will be discussed in Chapter 4.

Precharge logic gates are inherently less noisy because there is no short circuit (crowbar) current flowing from power to ground during each transition. The crowbar current is such that it has a large initial spike and a gradual rolloff, rather than a more moderate and constant level. This spike of crowbar current has the tendency to cause local power supply deviations. This is normally the source of ΔI noise. As less current flows, there is also less power dissipation in the logic gate. There is also less power dissipation at the input to the logic gate because the input capacitance is smaller. However, because the clock must be routed to many more places on the chip, there is increased power dissipation in the clock wires. Furthermore, if an input to a precharged gate is not switching, the output might switch with the clock, which increases overall power dissipation. Therefore, it is not clear what the impact on power dissipation is, and this has to be addressed on a case-by-case basis.

Another advantage of precharge logic design is that these circuits allow the designer to optimize the transistors for one edge of interest. This is in direct contrast to static circuits that will need to make their rising and falling output edge rates nearly equal.

Yet another advantage to precharge logic design is that these circuits can be expanded to include a latch mechanism in the logic circuitry without significantly slowing down the circuit. This is discussed in detail in Chapter 2 and also in Chapter 7.

A final advantage to precharge (domino) gates is that any resulting circuit will be glitch-free by construction. This is due to its single transition nature. As we will learn in **Section 1.6**, the only transition that a domino circuit can make during evaluation is that of a zero to one transition, on the output of the circuit.

It is now worthwhile to summarize the advantages and also mention a few disadvantages of precharge logic.

Advantages:

• Faster switching

• Less noise produced

• Less power dissipation (potentially)

• Smaller gate input capacitance

• Smaller layout area

• Optimized for one edge of interest

• Integrated latch mechanism possible

• Glitch-free by construction (domino)

• Great for high fan-in gates.

Disadvantages:

• Lower noise margin

• Difficulty with "time borrowing"

• Lack of inversions (domino)

• The need to route the clock to all gates

• Tricky design (charge sharing and leakage on dynamic nodes)

• More power dissipation (potentially)

• Difficult to interface with, require monotonic signals (domino)

• Require a precharge phase to prepare them for the next logic evaluation

• Minimum frequency of operation—cannot hold state in static mode.

In addition, it should be noted that precharge logic is a ratioless logic family, meaning that the slope of the transfer characteristic is not dependent on the ratio of the sizes of the PMOS and NMOS transistors.

*(Continues...)*

Excerpted fromSynchronous Precharge LogicbyMarek Smoszna. Copyright © 2012 by Elsevier Inc.. Excerpted by permission of Elsevier Science.

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