System-on-a-Chip Verification: Methodology and Techniques

by Prakash Rashinkar, Peter Paterson, Leena Singh

Overview

System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application.
System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter:

• Explanation of the objective involved in performing verification after a given design step;
• Features of options available;
• When to use a particular option;
• How to select an option; and
• Limitations of the option.
This exciting new book will be of interest to all designers and test professionals.

Product Details

ISBN-13:	9780792372790
Publisher:	Springer US
Publication date:	12/31/2000
Edition description:	2002
Pages:	372
Product dimensions:	6.10(w) x 9.25(h) x 0.03(d)

About the Author

Prakash Rashinkar Cadence Design Systems, Inc., San Jose, CA, USA.

Peter Paterson Cadence Design Systems, Inc., San Jose, CA, USA.

Leena Singh Cadence Design Systems, Inc., San Jose, CA, USA.

Read an Excerpt

Chapter 1: Introduction

This represents challenges over traditional design methodologies where different design disciplines (digital, AMS, embedded software (ESW)) could be designed in isolation with methodologies and tools specific to each discipline. In SOC, we now have these design disciplines coexisting within a single design, so the verification methodology has to deal with mixed digital and analog verification and mixed hardware/ESW verification. The tools must also deal with the added complexity of SOC devices, not only due to the increased gate counts but also the complex structures and algorithms implemented on these devices.

Figure 1-4 shows a topographical representation of the Bluetooth design to be used as an example throughout this book. In the example Bluetooth design, the radio frequency (RF) portion of the system resides off-chip. This is typical of today's highspeed communications technologies where substrate coupling issues make it impractical to mix RF and baseband circuits. Several emerging technologies, such as silicon-on-insulator and Silicon Germanium, offer the possibility of combining RF and baseband circuits in a single IC.

1.2 Verification Technology Options

The goal of verification is to ensure that the design meets the functional requirements as defined in the functional specification. Verification of SOC devices takes anywhere from 40 to 70 percent of the total development effort for the design. Some of the issues that arise are how much verification is enough, what strategies and technology options to use for verification, and how to plan for and minimize verification time. These issues challenge both verification engineers andverification solution providers.

A wide variety of verification technology options are available within the industry. These options can be broadly categorized into four classifications: simulationbased technologies, static technologies, formal technologies, and physical verification and analysis. The verification technology options currently available are described below. To achieve the SOC verification goals, a combination of these methods must be used.

1.2.1 Simulation Technologies

Simulation technologies include event-based and cycle-based simulators, transaction-based verification, code coverage, AMS simulation, HW/SW co-verification, accelerators, such as emulation, rapid prototype systems, hardware modelers, and hardware accelerators.

1.2.1.1 Event-based Simulators

Event-based simulators operate by taking events, one at a time, and propagating them through a design until a steady state condition is achieved. Any change in input stimulus is identified as an event.The design models include timing and functionality. A design element may be evaluated several times in a single cycle because the different arrival times of the inputs and the feedback of signals from downstream design elements. While this provides a highly accurate simulation environment, the speed of the execution depends on the size of the design and the level of activity within the simulation. For large designs, this can be slow.

Features: Provides an accurate simulation environment that is timing-accurate, and it is easy to detect glitches in the design.

Limitations: The speed depends on the size of the design and the level of activity within the simulation. If the designs are large, the simulation speed may be slow. The speed is limited because event-based simulators use complex algorithms to schedule events, and they evaluate the outputs multiple times.

1.2.1.2 Cycle-based Simulators

Cycle-based simulators have no notion of time within a clock cycle. They evaluate the logic between state elements and/or ports in the single shot. Because each logic element is evaluated only once per cycle, this can significantly increase the speed of execution, but this can lead to simulation errors. Cycle-based simulators only function on synchronous logic.

Features: Provides speeds of 5x to 100x times that of event-based simulators. The simulation speed can be up to 1000 cycles per second for large designs. Best suited for designs requiring large simulation vectors, such as microprocessors, application-specific integrated chips (ASIC), and SOCs.

Limitations: Cannot detect glitches in the design, since they respond only to the clock signal. Also they do not take the timing of the design into consideration, therefore, timing verification needs to be performed using a static-timing analysis tool.

1.2.1.3 Transaction-based Verification

Transaction-based verification allows simulation and debug of the design at the transaction level, in addition to the signal/pin level. All possible transaction types between blocks in a system are created and systematically tested. Transactionbased verification does not require detailed testbenches with large vectors.

The bus function model (BFM) is used in transaction-based verification. BFMs provide a means of running the transactions on the hardware design interfaces. They drive signals on the interconnects according to the requirements of the interface protocols. They can be easily authored in standard hardware description languages (HDL) and C++.

Features: Enhances the verification productivity by rasing the level of abstraction to transaction level, instead of the signal/pin level. Self-checking and directed random testing can be easily performed.

1.2.1.4 Code Coverage

Code coverage analysis provides the capability to quantify the functional coverage that a particular test suite achieves when applied to a specific design. This can be at the individual block level or the full-chip level. The analysis tools provide a value for the percentage coverage of each attribute being assessed, and a list of untested or partially tested areas of the design.

Code coverage analysis is performed on the register-transfer level (RTL) views of the design. It assesses the various types of coverage including: statement, toggle, finite-state-machine (FSM) arc, visited state, triggering, branch, expression, path, and signal.

Features: Provides an assessment of the quality of the test suites. It also identifies untested areas of a design.

1.2.1.5 HW/SW Co-verification

In HW/SW co-verification, integration and verification of the hardware and software occurs concurrently. The co-verification environment provides a graphical user interface (GUI) that is consistent with the current hardware simulators and software emulators/debuggers that are used by the hardware and software project development teams....

Table of Contents

System-level Verification.- Block-level Verification.- Analog/Mixed Signal Simulation.- Simulation.- Hardware/Software Co-verification.- Static Netlist Verification.- Physical Verification and Design Sign-off.

Editorial Reviews

The combination of previously separate elements into one lone chip presents engineers with challenges to traditional verification approaches. This guide provides a series of tools and techniques that can be employed for system-on-chip (SOC) verification and design error reduction. The authors, who work for Cadence Design Systems, walk through system level and block verification, simulation, hardware/software co-verification, static netlist verification, and physical verification technologies. Particular attention is paid to newer techniques<-->such as testbench migration, formal model and equivalence checking, linting, and code coverage<-->and the material is illustrated by examples based on a Bluetooth SOC design. Annotation c. Book News, Inc., Portland, OR (booknews.com)

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