Paperback(1 ED)
-
PICK UP IN STORECheck Availability at Nearby Stores
Available within 2 business hours
Related collections and offers
Overview
- What components are needed to build a T1 line, and how those components interact to transmit data effectively
- How to use standardized link layer protocols to adapt the T1 physical layer to work with data networks
- How to troubleshoot problems and work with the telephone company, equipment manufacturers, and Internet service providers
Product Details
| ISBN-13: | 9780596001278 |
|---|---|
| Publisher: | O'Reilly Media, Incorporated |
| Publication date: | 08/01/2001 |
| Edition description: | 1 ED |
| Pages: | 304 |
| Product dimensions: | 7.00(w) x 9.19(h) x 0.70(d) |
About the Author
Read an Excerpt
Chapter 5: Timing, Clocking, and Synchronization in the T-carrier System
Time is the extension of motion.
--Zeno
Faster networks depend on accurate timing. As the number of bits per second increases, the time in which to look for any particular bit decreases. Getting both sides to agree on timing becomes more difficult at higher speeds. Synchronous networking is largely about distribution of accurate timing relationships.
A Timing Taxonomy
Synchronous communications do not depend on start and stop flags to mark the beginning and end of meaningful data. Instead, the network constantly transmits data and uses a separate clock signal to determine when to examine the incoming stream to extract a bit. Distributing clock information to network nodes is one of the major challenges for synchronous network designers. Three major types of timing are used on networks: asynchronous, synchronous, and plesiochronous. All three terms derive from the Greek word kronos, meaning time. The three differ in how they distribute timing information through the network.
Asynchronous systems do not share or exchange timing information. Each network element is timed from its own free-running clock. Analog modems are asynchronous because timing is derived from start and stop bits in the data stream. Free-running clocks are adequate for dial-up communications because the time slots are much longer than on higher-speed digital networks.
Synchronous systems distribute timing information from an extremely accurate primary system clock. Each network element inherits its timing from the primary clock and can trace its lineage to the common shared clock. When AT&T operated the U.S. telephone network, the system derived its timing from the primary reference source (PRS), a cluster of cesium clocks located in Hillsboro, Missouri.
Synchronous networks may have several layers of accuracy, but the important feature is that each clock can trace timing to a single reference source. In the case of the Bell system, the primary source was labeled Stratum 1. Less-accurate devices were in higher-numbered strata. Tandem offices, also called toll offices, serviced the long-haul portions of the telephone network and were located in Stratum 2. Local switching offices were located in Stratum 3, with end-user devices such as CSU/DSUs in Stratum 4.
Figure 5-1 sketches the basic system, along with its end goal: distribution of accurate timing to peers at each stratum level. The master PRS at the top of the picture is the source of all timing goodness throughout the network. The network distributes timing information from the primary reference to the toll offices and from the toll offices to local switching offices. Customers attach to the local switching offices. Because timing information even at the lowly customer-equipment stratum is derived from the master clock, two pieces of customer equipment at the end of a T1 link between different local offices can operate within the strict timing tolerances required with 648-nanosecond bit times.
Maintaining a single network timing source is extremely expensive, and the timing distribution must be carefully engineered. Having only one timing source did not fit into the model of the post-divestiture telecommunications landscape in the U.S.
Plesiochronous networks are networks in which the elements are timed by separate clocks, which are very precise and operate within narrow tolerances. Within one telco's network, there may be multiple "primary" (Stratum 1) clocks; each telco maintains its own set of timing information.1 For this reason, the U.S. telephone network is really a plesiochronous network. For contrast with a synchronous network, Figure 5-2 illustrates a plesiochronous network.
Figure 5-2 divides the network into its timing components on top and the data-transport facilities on the bottom. It also shows the facilities of two different carriers, one on the left and one on the right. A T1 transports data between the customer CSU/DSU on the left and the CSU/DSU on the right. Both telcos maintain their own primary reference sources to feed timing information to switching offices and to the devices making up the transport facilities. Even though the T1 is provided by two different carriers, precise timing tolerances allow them to cooperate in providing the T1 without needing a single shared (and trusted) source of timing information.
T-carrier systems are technically known as the plesiochronous digital hierarchy (PDH). In practice, though, the distinction between plesiochronous and synchronous is a hair-splitting one. "Synchronous" has acquired a connotation of describing any system that depends on extremely accurate timing, and the T-carrier system is occasionally referred to as the synchronous digital hierarchy (SDH). In mafsny cases, the two are combined into one acronym: PDH/SDH.
T1 Circuit Timing
CSU/DSUs are like bridges. They have one interface in telco territory and one interface in data-communications territory. Both are serial interfaces that make use of tight timing tolerances. Appropriate configuration of the CSU/DSU to work within the timing straitjacket is essential.
Receive Clock Inference on the Network Interface
In the T1 world, clock signals are not transmitted separately from the data stream. Instead, receivers must extract the clock from the data signal based on the stream itself. Each bit time slot is 648 nanoseconds. Pulses are transmitted with a 50% duty cycle, meaning that for the middle half of the time slot, the voltage is at its peak. Based on these characteristics, the receiving CSU/DSU infers time slot boundaries from incoming pulses. Ideally, each pulse comes in the middle of a time slot, so finding time-slot boundaries is simply a matter of going 324 ns in each direction. Figure 5-3 illustrates clock inference from pulse reception.
In practice, of course, things are never quite as simple, and CSU/DSUs must compensate for a variety of non-ideal conditions. Clock signals may exhibit both short-term and long-term irregularities in their timing intervals. Short-term deviation is called jitter, and long-term deviation is referred to as wander.
TIP: Timing on the T1 network interface from the telco is implicit and based on the content of the pulse stream. On the other hand, the serial circuit that connects the CSU/DSU to the router makes use of explicit timing. V.35, for example, includes two pairs (four leads) for sending timing signals and one pair (two leads) for receiving timing.
Transmit Clocking at the Network Interface
At the interface to the telco network, clocking on the received data is based on inferring where the bit times fall. The CSU/DSU does not send an explicit clock for use with transmitted data, but uses internal circuitry to determine when to send a pulse. The internal clocking circuitry can typically operate in one of three modes, which go by different names for different vendors. Descriptively speaking, the typical modes of operation are to derive the transmit clock from the telco, to use an internally generated timing signal, or to take the transmit clock from the attached DTE. Of the three options, the first two are by far the most common in data-transmission applications.
Master/slave timing (also called network or loop timing)
In master/slave timing, the CSU/DSU takes its timing from the telco network. The telco network maintains an extremely accurate timing source and uses that to send pulses to customer locations. At the customer CSU/DSU, the receive clock is extracted from the incoming pulses. In master/slave timing, the extracted receive clock is used for the transmit clock on the network interface, as shown in Figure 5-4.
Master/slave timing ensures that the less-accurate clock in the customer premises equipment does not drift significantly, relative to the telco's accurate timing system. Several sources may drive the telco transmit clock. One common source is the building-integrated timing supply (BITS), which ensures that all the equipment in the CO is running from the same signal. BITS can be linked to an external clock, illustrated in Figure 5-4 as the PRS. At the customer side of the link, the CSU/DSU extracts the receive clock, rather than relying on an internal oscillator in the CSU/DSU. Master/slave timing is also called loop timing because the clock is extracted from signals on the digital loop, or network timing because the clock source is from the telco network interface.
Internal timing
Internal timing uses an internal oscillator in the CSU/DSU as the transmit clock source. No special measures are taken to ensure that the timing of transmitted pulses matches the timing of received pulses because the two operations are logically independent, as Figure 5-5 illustrates.
All circuits must have one timing source. In most cases, the telco will supply timing because the entire telco network must operate with unified timing to deliver the T1 circuit. In some cases, however, a simple copper wire pair can be leased from the telco. For spans with less than 30 dB attenuation, an unrepeatered copper pair can cost much less than a full-service line. In private-line applications, one end of the line must provide the clock, as Figure 5-6 shows. The remote end is set to loop timing, so the remote transmit clock is derived from the local transmit clock.
Clocking at the Data Port
Data ports on CSU/DSUs are synchronous serial ports. CSU/DSUs transmit data as a varying voltage on the line, with a high voltage representing one and a zero voltage used for zero. A second signal, the clock signal, triggers a voltage measurement and extracts a bit from the voltage stream. Figure 5-7 illustrates the use of the explicit clock signal on a synchronous serial port.
In Figure 5-7, the external clock signal triggers a measurement when the clock signal goes from a low voltage to a high voltage. Aligning the clock signal with the voltage plateaus is important. Ideally, the clock signal should trigger a voltage measurement at the middle of the bit time. If the clock signal falls too close to a voltage transition, the reading will be unreliable....
Table of Contents
- Preface
- Chapter 1: History of the U.S. Telephone Network
- Chapter 2: T1 Architectural Overview
- Chapter 3: Basic Digital Transmission on Telephone Networks
- Chapter 4: Multiplexing and the T-carrier Hierarchy
- Chapter 5: Timing, Clocking,and Synchronization in the T-carrier System
- Chapter 6: Mysteries of theCSU/DSU
- Chapter 7: Connecting the Umbilicus: GettingT1 Connectivity
- Chapter 8: High-Level Data Link Control Protocol (HDLC)
- Chapter 9: PPP
- Chapter 10: Frame Relay
- Chapter 11: T1 Troubleshooting
- Access Aggregation with cT1 andISDN PRI
- Multilink PPP
- T1 Performance Monitoring
- SNMP
- Cable Pinouts and Serial Information
- Reference
- Glossary
- Colophon