Test Generation of Crosstalk Delay Faults in VLSI Circuits
This book describes a variety of test generation algorithms for testing crosstalk delay faults in VLSI circuits. It introduces readers to the various crosstalk effects and describes both deterministic and simulation-based methods for testing crosstalk delay faults. The book begins with a focus on currently available crosstalk delay models, test generation algorithms for delay faults and crosstalk delay faults, before moving on to deterministic algorithms and simulation-based algorithms used to test crosstalk delay faults. Given its depth of coverage, the book will be of interest to design engineers and researchers in the field of VLSI Testing.
1133662516
Test Generation of Crosstalk Delay Faults in VLSI Circuits
This book describes a variety of test generation algorithms for testing crosstalk delay faults in VLSI circuits. It introduces readers to the various crosstalk effects and describes both deterministic and simulation-based methods for testing crosstalk delay faults. The book begins with a focus on currently available crosstalk delay models, test generation algorithms for delay faults and crosstalk delay faults, before moving on to deterministic algorithms and simulation-based algorithms used to test crosstalk delay faults. Given its depth of coverage, the book will be of interest to design engineers and researchers in the field of VLSI Testing.
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Test Generation of Crosstalk Delay Faults in VLSI Circuits

Test Generation of Crosstalk Delay Faults in VLSI Circuits

Test Generation of Crosstalk Delay Faults in VLSI Circuits

Test Generation of Crosstalk Delay Faults in VLSI Circuits

Overview

This book describes a variety of test generation algorithms for testing crosstalk delay faults in VLSI circuits. It introduces readers to the various crosstalk effects and describes both deterministic and simulation-based methods for testing crosstalk delay faults. The book begins with a focus on currently available crosstalk delay models, test generation algorithms for delay faults and crosstalk delay faults, before moving on to deterministic algorithms and simulation-based algorithms used to test crosstalk delay faults. Given its depth of coverage, the book will be of interest to design engineers and researchers in the field of VLSI Testing.

Product Details

ISBN-13: 9789811347849
Publisher: Springer Nature Singapore
Publication date: 12/20/2018
Edition description: Softcover reprint of the original 1st ed. 2019
Pages: 156
Product dimensions: 6.10(w) x 9.25(h) x (d)

About the Author

Dr. S. Jayanthy is a Professor at the Department of Electronics and Communication Engineering, Sri Ramakrishna Engineering College, Coimbatore, India. She received her Master’s and PhD from PSG College of Technology and Anna University, Chennai respectively. Prof. Jayanthy’s research interests are in VLSI Design & Testing, Genetic Algorithms and Embedded Systems. With more than 20 years of teaching experience, she has published 2 chapters and more than 40 research papers in journals and for national and international conferences and has organized a number of workshops and national conferences in the areas of VLSI, Embedded systems and IOT. She is a life member of Indian Society for Technical Education and Institution of Electronics and Telecommunication Engineers

Dr. M.C. Bhuvaneswari is an Associate Professor at the Department of Electrical and Electronics Engineering, PSG College of Technology, Coimbatore, India. She received her BE in Electronics and Communications Engineering from Madras University, and her ME and PhD from Bharathiar University. Her research interests include Applied Electronics, VLSI Design and Testing, Genetic Algorithms, Digital System Design, and Microprocessors. She has published a book on VLSI and Embedded systems (2015) and authored more than 90 research papers in journals and for national and international conferences. She is a life member of Indian Society for Technical Education, Institute of Engineers (India), Computer Society of India and Systems Society of India. Prof Bhuvaneswari was honored with Dakshinamoorthy award instituted by PSG College of Technology for Teaching Excellence in the year 2010

Table of Contents

Chapter 1. Background and Review of Crosstalk Delay Fault Models and the Crosstalk Effects.- Chapter 2. Review of Test Generation Techniques for Crosstalk Delay Faults.- Chapter 3. An Automatic Test Pattern Generation Method for Crosstalk Delay Faults Using Modified PODEM and FAN Algorithm.- Chapter 4. An Automatic Test Pattern Generation Method for Crosstalk Delay Faults using Single-Objective Genetic Algorithm.- Chapter 5. An Automatic Test Pattern Generation Method for Crosstalk Delay Faults Using Single-Objective Particle Swarm Optimization.- Chapter 6. Simulation of Asynchronous Sequential Circuits using Fuzzy Delay Model.- Chapter 7. Simulation Based Test Generation for Crosstalk Delay Faults in Asynchronous Sequential Circuits.

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