- Shopping Bag ( 0 items )
Ships from: Newton, MA
Usually ships in 1-2 business days
Ships from: Chicago, IL
Usually ships in 1-2 business days
VDHL is the standard language for describing the structure and function of digital systems. This authoritative guide illustrates the importance of the VDHL-93 standard in designing high-speed digital systems. Requiring only a minimal background of Pascal or FORTRAN programming, this is an excellent tutorial for anyone in computer architecture, computer systems engineering and CAD.
if we are to discuss the topic of modeling digital systems, we first need to agree on what a digital system is. Different engineers would come up with different definitions, depending on their background and the field in which they were working. Some may consider a single VLSI circuit to be a self-contained digital system. Others might take a larger view and think of a complete computer, packaged in a cabinet with peripheral controllers and other interfaces.
For the purposes of this book, we include any digital circuit that processes or stores information as a digital system. We thus consider both the system as a whole and the various parts from which it is constructed. Thus our discussions cover a range of systems from the low-level gates that make up the components to the top-level functional units.
If we are to encompass this range of views of digital systems, we must recognize the complexity with which we are dealing. It is not humanly possible to comprehend such complex systems in their entirety. We need to find methods of dealing with the complexity, so that we can, with some degree of confidence, design components and systems that meet their requirements.
The most important way of meeting this challenge is to adopt a systematic methodology of design. If we start with a requirements document for the system, we can design an abstract structure that meets the requirements. We can then decompose this structure into a collection of components that interact to perform the same function. Each of these components can in turn be decomposed until we get to a level where we have some ready-made, primitive components that perform a required function. The result of this process is a hierarchically composed system, built from the primitive elements.
The advantage of this methodology is that each subsystem can be designed independently of others. When we use a subsystem, we can think of it as an abstraction rather than having to consider its detailed composition. So at any particular stage in the design process, we only need to pay attention to the small amount of information relevant to the current focus of design. We are saved from being overwhelmed by masses of detail.
We use the term model to mean our understanding of a system. The model represents that information which is relevant and abstracts away from irrelevant detail. The implication of this is that there may be several models of the same system, since different information is relevant in different contexts. One kind of model might concentrate on representing the function of the system, whereas another kind might represent the way in which the system is composed of subsystems. We will come back to this idea in more detail in the next section.
There are a number of important motivations for formalizing this idea of a model. First, when a digital system is needed, the requirements of the system must be specified. The job of the engineers is to design a system that meets these requirements. To do that, they must be given an understanding of the requirements, hopefully in a way that leaves them free to explore alternative implementations and to choose the best according to some criteria. One of the problems that often arises is that requirements are incompletely and ambiguously spelled out, and the customer and the design engineers disagree on what is meant by the requirements document. This problem can be avoided by using a formal model to communicate requirements.
A second reason for using formal models is to communicate understanding of the function of a system to a user. The designer cannot always predict every possible way in which a system may be used, and so is not able to enumerate all possible behaviors. If the designer provides a model, the user can check it against any given set of inputs and determine how the system behaves in that context. Thus a formal model is an invaluable tool for documenting a system.
A third motivation for modeling is to allow testing and verification of a design using simulation. If we start with a requirements model that defines the behavior of a system, we can simulate the behavior using test inputs and note the resultant outputs of the system. According to our design methodology, we can then design a circuit from subsystems, each with its own model of behavior. We can simulate this- composite system with the same test inputs and compare the outputs with those of the previous simulation. If they are the same, we know that the composite system meets the requirements for the cases tested. Otherwise we know that some revision of the design is needed. We can continue this process until we reach the bottom level in our design hierarchy, where the components are real devices whose behavior we know. Subsequently, when the design is manufactured, the test inputs and outputs from simulation can be used to verify that the physical circuit functions correctly. This approach to testing and verification of course assumes that the test inputs cover all of the circumstances in which the final circuit will be used. The issue of test coverage is a complex problem in itself and is an active area of research.
A fourth motivation for modeling is to allow formal verification of the correctness of a design. Formal verification requires a mathematical statement of the required function of a system. This statement may be expressed in the notation of a formal logic system, such as temporal logic. Formal verification also requires a mathematical definition of the meaning of the modeling language or notation used to describe a design. The process of verification involves application of the rules of inference of the logic system to prove that the design implies the required function. While formal verification is not yet in everyday use, it is an active area of research. There have already been significant demonstrations of formal verification techniques in real design projects, and the promise for the future is bright.
One final, but equally important, motivation for modeling is to allow automatic synthesis of circuits. If we can formally specify the function required of a system, it is in theory possible to translate that specification into a circuit that performs the function. The advantage of this approach is that the human cost of design is reduced, and engineers are free to explore alternatives rather than being bogged down in design detail. Also, there is less scope for errors being introduced into a design and not being detected. If we automate the translation from specification to implementation, we can be more confident that the resulting circuit is correct.
The unifying factor behind all of these arguments is that we want to achieve maximum reliability in the design process for minimum cost and design time. We need to ensure that requirements are clearly specified and understood, that subsystems are used correctly and that designs meet the requirements. A major contributor to excessive cost is having to revise a design after manufacture to correct errors. By avoiding errors, and by providing better tools for the design process, costs and delays can be contained.
1.2 Domains and Levels of Modeling
In the previous section, we mentioned that there may be different models of a system, each focussing on different aspects. We can classify these models into three domains: function, structure and geometry. The functional domain is concerned with the operations performed by the system. In a sense, this is the most abstract domain of description, since it does not indicate how the function is implemented. The structural domain deals with how the system is composed of interconnected subsystems. The geometric domain deals with how the system is laid out in physical space.
Each of these domains can also be divided into levels of abstraction. At the top level, we consider an overview of function, structure or geometry, and at lower levels we introduce successively finer detail. Figure 1-1 (devised by Gajski and Kuhn, see reference [61) represents the domains on three independent axes, and represents the levels of abstraction by the concentric circles crossing each of the axes....
1 Fundamental Concepts 1
2 Scalar Data Types and Operations 31
3 Sequential Statements 65
4 Composite Data Types and Operations 95
5 Basic Modeling Constructs 137
6 Subprograms 207
7 Packages and Use Clauses 245
8 Resolved Signals 267
9 Predefined and Standard Packages 293
10 Case Study: A Pipelined Multiplier Accumulator 337
11 Aliases 355
12 Generics 365
13 Components and Configurations 417
14 Generate Statements 449
15 Access Types 479
16 Files and Input/Output 499
17 Case Study: A Package for Memories 535
18 Test Bench and Verification Features 559
19 Shared Variables and Protected Types 585
20 Attributes and Groups 603
21 Design for Synthesis 633
22 Case Study: System Design Using the Gumnut Core 669
23 Miscellaneous Topics 733
A Standard Packages 793
B VHDL Syntax 841
C Answers to Exercises 859
by Paul Mencbini
Research Triangle Park, North Carolina
Digital electronic systems are increasing exponentially in their complexity over time. This fact, coupled with decreasing product lifetimes and increasing reliability requirements, has forced designers to dramatically increase their productivity and the quality of their designs.
VHDL was developed in response to these trends. Borrowing complexity management and error detection techniques from the software engineering world, VHDL was developed to eliminate irrelevant detail, allow technology-independent description, catch errors earlier, and promote portable and interoperable models from the gate to the system level.
In response, EDA tools have been designed to take an ever-greater share of the burden from designers. A single representation medium can now drive design processes from specification down to detailed digital design.
Originally developed as the United States Department of Defense's standard hardware description language (HDL), VHDL has evolved through two additional rounds of IEEE standardization into one of the two preeminent HDLs in use throughout the world. Continued development in the areas of detailed timing models, synthesis directives, analog capabilities, and so forth mean the VHDL will continue to provide the expressive facilities needed by state-of-the-art designs well into the next century. New tools leveraging on VHDL's precise definition continue to be introduced and offer increased simulation performance, increased synthesis capabilities, and entirely new capabilities such as the formal verification of the functional equivalence of models.
Because VHDL usesconcepts not commonly found in hardware description, designers approaching VHDL for the first time need a sure guide to the features using these concepts. One of the few books on VHDL that does not rely heavily on experience with programming languages, A Designer's Guide to VHDL is ideal for the nonprogrammer wishing to learn VHDL.
This book explores in detail the latest version of VHDL, VHDL-93 (IEEE Std. 1076-1993). Assuming no prior knowledge of VHDL, Professor Ashenden walks the reader through VHDL, first addressing simple modeling issues, then moving on to the more complex. As VHDL contains many features, the reader is greatly aided by the inclusion of four fully worked case studies. These case studies put VHDL's features in context and show how they work in concert to model digital systems of varying levels of complexity and varying levels of detail.
Appendices cover the use of VHDL in synthesis, as well as other standards built upon the VHDL framework. As an aid to the experienced user of VHDL, other appendices contain syntax summaries and a list of differences from the initial IEEE standard, IEEE Std. 1076-1987.
Welcome to VHDL!
Posted August 16, 2000
The author details differences between VHDL '87 and '93 and provides many working examples of both(can also download all source code in book from his website). The technical coverage of VHDL constructs helps develop a deeper understanding of effectively writing good code. In particular, his coverage of text I/O goes well beyond the typical treatment in many VHDL books and is extremely useful. As with most VHDL books, about the only weaknesses are coverage of VITAL and methodologies for writing lean, efficient code that results hardware with these attributes.Was this review helpful? Yes NoThank you for your feedback. Report this reviewThank you, this review has been flagged.
Posted August 2, 2000
The basic problem with this book is the professor focuses on the language constructs. Many of the examples are code snippets which will not work or compile when typed as written. Only the case studies show complete code examples. For the working engineer trying to find examples of working functions the book is lacking. I found the section on textio particularly frustrating, especially since this would have been useful for testbenches.Was this review helpful? Yes NoThank you for your feedback. Report this reviewThank you, this review has been flagged.