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The Student's Guide to VHDL / Edition 1

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Overview

VHDL is a language for describing digital electronic systems. A vital, efficient step in the system design process, VHDL allows for the design and simulation of a hardware system prior to it actually being manufactured.
This new book provides a tutorial introduction to the fundamental modeling features of VHDL and shows how the features are used for the design of digital systems.

Offering the same clear, accessible style as The Designer's Guide to VHDL, The Student's Guide is designed as a main text for introductory VHDL courses, and as a supplementary text for courses that require VHDL-based project work, such as computer architecture, digital design, and digital logic courses. This new condensed text also serves as a quick, self-teaching guide for practicing engineers who need to learn only the basics of VHDL.

* On-line resources include code for case studies.
* Numerous exercises that are coded for difficulty and expected solution time.
• Solutions to the level one exercises are included in the book for self-testing.
* An appendix citing the differences between the 1987 standard and the 1993 standard which is described in the book.

VDHL is the standard language for describing the structure and function of digital systems. This authoritative guide illustrates the importance of the VDHL-93 standard in designing high-speed digital systems. Requiring only a minimal background of Pascal or FORTRAN programming, this is an excellent tutorial for anyone in computer architecture, computer systems engineering and CAD.

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Editorial Reviews

Booknews
Written for engineering students, this introduction to VHDL (a language for describing digital electronic systems for the pre- manufacturing design of hardware systems) covers such topics as scalar data types, sequential statements, composite data types, modeling constructs, subprograms, packages and use clauses, resolved signals, generic constants, and components and configurations. Annotation c. by Book News, Inc., Portland, Or.
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Product Details

  • ISBN-13: 9781558605206
  • Publisher: Elsevier Science
  • Publication date: 1/15/1998
  • Series: Systems on Silicon Series
  • Edition description: Older Edition
  • Edition number: 1
  • Pages: 312
  • Product dimensions: 7.44 (w) x 9.18 (h) x 0.74 (d)

Meet the Author

Peter J. Ashenden received his B.Sc.(Hons) and Ph.D. from the University of Adelaide, Australia. He was previously a senior lecturer in computer science and is now a Visiting Research Fellow at the University of Adelaide. His research interests are computer organization and electronic design automation. Dr. Ashenden is also an independent consultant specializing in electronic design automation (EDA). He is actively involved in IEEE working groups developing VHDL standards, is the author of The Designer's Guide to VHDL and The Student's Guide to VHDL and co-editor of the Morgan Kaufmann series, Systems on Silicon. He is a senior member of the IEEE and a member of the ACM.

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Read an Excerpt

From Chapter 7: Packages and Use Clauses

...Subprograms in Package Declarations

Another kind of declaration that may be included in a package declaration is a subprogram declaration—either a procedure or a function declaration. This ability allows us to write subprograms that implement useful operations and to call them from a number of different modules. An important use of this feature is to declare subprograms that operate on values of a type declared by the package. This gives us a way of conceptually extending VHDL with new types and operations, so-called abstract data types.

An important aspect of declaring a subprogram in a package declaration is that we only write the header of the subprogram, that is, the part that includes the name and the interface list defining the parameters (and result type for functions). We leave out the body of the subprogram. The reason for this is that the package declaration, as we mentioned earlier, provides only the external view of the items it declares, leaving the implementation of the items to the package body. For items such as types and signals, the complete definition is needed in the external view. However, for subprogram. As users of a subprogram, we need not be concerned with how it achieves its effect or calculates its result. This is an example of a general principle called information hiding: making an interface visible but hiding the details of implementation. To illustrate this idea, suppose we have a package declaration that defines a bit-vector subtype:

subtype word32 is bit_vector(31 downto 0);

We can include in the package a procedure to do addition onWord32 values that represent signed integers. The procedure declaration in the package declaration is:

procedure add ( a, b : in word32; result : out word32; overflow : out boolean );

Note that we do not include the keyword is or any of the local declarations or statements needed to perform the addition. These are deferred to the package body. All we include is the description of the formal parameters of the procedure. Similarly, we might include a function to perform an arithmetic comparison of two word32 values:

function "<" ( a, b : in word 32 ) return boolean;

Again, we omit the local declarations and statements, simply specifying the formal parameters and the result type of the function.

Constants in Package Declarations

Just as we can apply the principle of information hiding to subprograms declared in a package, we can also apply it to constants declared in a package. The external view of a constant is just its name and type. We need to know these in order to use it, but we do not actually need to know its value. This may seem strange at first, but if we recall that the idea of introducing constant declarations in the first place was to avoid scattering literal values throughout a model, it makes more sense. We defer specifying the value of a constant declared in a package by omitting the initialization expression, for example:

constant max_buffer_size : positive;

This defines the constant to be a positive integer value. However, since we cannot see the actual value, we are not tempted to write the value as an integer literal in a model that uses the package. The specification of the actual value is deferred to the package body; where it is not visible to a model that uses the package. Given the above deferred constant in a package declaration, the corresponding package body must include the full constant declaration, for example:

constant max_buffer_size : positive := 4096;

Note that we do not have to defer the value in a constant declaration—it is optional...

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Table of Contents

Preface

1 Fundamental Concepts

2 Scalar Data Types and Operations

3 Sequential Statements

4 Composite Data Types and Operations

5 Basic Modeling Constructs

6 Subprograms

7 Packages and Use Clauses

8Resolved Signals

9 Generic Constants

10 Components and Configurations

A The Predefined Package Standard

B IEEE Standard 1164

C VHDL Syntax

D Differences Between VHDL-87 and VHDL-93

E Answers to Exercises

References

Index

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Sort by: Showing all of 2 Customer Reviews
  • Anonymous

    Posted June 18, 2005

    I liked it a lot

    I found this book very useful, as a learning tool, and as a reference. The author demonstrates a good command of the language and the methodologies behind it, but he isn't too far gone into it to be able to step aside and show you what's happening. Few books will answer every question, but this took care of most of mine. This book was a bible for several of the digital design classes I took in college.

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  • Anonymous

    Posted December 12, 2002

    Look for better

    The author starts off by confusing the reader as much as possible from the very beginning, and his writing style is erratic and unorganized. A ton of outside sources will be needed to write code in VHDL, as the proper style and format of even simple code is skewed and lost in the translation. Not recommended as a first book or primer, even though the title suggests it.

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