The Verilog� Hardware Description Language

by Donald E. Thomas, Philip R. Moorby

Overview

The Verilog language is a hardware description language which provides a means of specifying a digital system at a wide range of levels of abstraction. The language supports the early conceptual stages of design with its behavioral level of abstraction, and the later implementation stages with its structural level of abstraction. The language provides hierarchical constructs, allowing the designer to control the complexity of a description. Verilog was originally designed in the winter of 1983/84 as a proprietary verification/simulation product. Since then, several other proprietary analysis tools have been developed around the language, including a fault simulator and a timing analyzer; the language being instrumental in providing consistency across these tools. Now, the language is openly available for any tool to read and write. This book introduces the language. It is sometimes difficult to separate the language from the simulator tool because the dynamic aspects of the language are defined by the way the simulator works. Where possible, we have stayed away from simulator-specific details and concentrated on design specification, but have included enough information to be able to have working executable models. The book takes a tutorial approach to presenting the language.

Product Details

ISBN-13:	9781461367840
Publisher:	Springer US
Publication date:	11/05/2012
Edition description:	Softcover reprint of the original 1st ed. 1991
Pages:	223
Product dimensions:	6.10(w) x 9.25(h) x 0.02(d)

About the Author

Donald E. Thomas Electrical & Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA

Philip R. Moorby Synapix Inc., Lowell, MA, USA

Read an Excerpt

Chapter 6: Logic Synthesis

Our view of the language so far has been toward modeling and simulating logic hardware. We have presented language constructs that can be used to specify the intricate functionality and timing of a circuit. Using this approach, we can simulate a design using timing parameters based on circuits that have been placed and routed, giving great confidence in the results of the simulation. In this chapter, we consider an alternate view of the language: synthesis. When using the language as an input specification for synthesis, the concern is specifying a functionally correct system while allowing a synthesis CAD tool to design the final gate level structure of the system. These views of the language are complementary. However, care must be taken in writing a description that will be used in both simulation and synthesis.

6.1 Overview of Synthesis

The predominate synthesis technology in use today is logic synthesis. A system is specified at the register-transfer level of design, and, by using logic synthesis tools, a gate level implementation of the system can be obtained. The synthesis tools are capable of optimizing a design with respect to various constraints, including timing and/or area. They use a technology library file to specify the components to be used in the design. Writing Verilog specifications for logic synthesis tools will be discussed in this chapter.

6.1.1 Register-Transfer Level Systems

A register- transfer level description may contain different features; parts of the description may be purely combinational while others may specify sequential elements such as latches and flip flops. There may also be a finite state machine description, specifying a state transition graph.

A logic synthesis tool compiles a register-transfer level design using two main phases. The first is a technology independent phase where the design is read in and manipulated without regard to the final implementation technology. In this phase, major simplifications in the combinational logic may be made. The second phase is technology mapping where the design is transformed to match the components in a component library. If there are only two-input gates in the library, the design is transformed so that each logic function is implementable by a component in the library. Indeed, synthesis tools can transform one gate level description into another, providing the capability of redesigning a circuit when a new technology library is used.

The attraction of a logic synthesis CAD tool is that it aids in a fairly complex design process. (After all, did your logic design professor ever tell you what to do when the Karnaugh map had more than five or six variables!) These tools target large combinational design and different technology libraries, providing implementation trade-offs in time and area. Further, they promise functional equivalence of the initial specification and its resulting implementation. Given the complexity of this level of design, these tools improve the productivity of designers in many common design situations.

To obtain this increased productivity, we must specify our design in a way that it can be simulated for functional correctness and then synthesized. Whereas the earlier parts of this book focussed on the semantics of the full language and how it can be used to model intricate timing and behavior, this chapter discusses methods of describing register-transfer level systems for input to logic synthesis tools.

6.1.2 Disclaimer

The first part of this chapter defines what a synthesizable description for logic synthesis is. There are behaviors that we can describe but that common logic synthesis tools will not be able to design. (Or they may design something you'd want your competitor to implement!) Since synthesis technology is still young, and the task of mapping an arbitrary behavior on to a set of library components is complex, arbitrary behavior specifications are not allowed as inputs to logic synthesis tools. Thus, only a subset of the language may be used for logic synthesis, and the style of writing a description using that subset is restricted. The first part of this chapter describes the subset and restrictions commonly found in logic synthesis specification today. As logic synthesis technology matures, the set of allowable constructs will probably expand and the style restrictions will probably lessen; -hey both have evolved over the last several years....

Table of Contents

1. Verilog — A Tutorial Introduction.- 1.1 Describing Digital Systems.- 1.2 Getting Started.- 1.2.1 A Structural Description.- 1.2.2 Simulating the NAND Latch.- 1.3 Module Hierarchy.- 1.3.1 The Counter.- 1.3.2 Components of the Counter.- 1.3.3 A Clock for the System.- 1.3.4 Tying the Whole Circuit Together.- 1.4 Behavioral Modeling.- 1.4.1 A Behavioral Model of the m16 Counter.- 1.4.2 Mixing Structure and Behavior.- 1.4.3 Assignment Statements.- 1.4.4 Mixing Behavioral and Structural Descriptions.- 1.5 Summary.- 1.6 Exercises.- 2. Behavioral Modeling Constructs.- 2.1 Process Model.- 2.2 If-Then-Else.- 2.2.1 Where Does The ELSE Belong?.- 2.2.2 The Conditional Operator.- 2.3 Loops.- 2.3.1 Four Basic Loop Statements.- 2.3.2 Exiting Loops on Exceptional Conditions.- 2.4 Multi-way branching.- 2.4.1 If-Else-If.- 2.4.2 Case.- 2.4.3 Comparison of Case and If-Else-If.- 2.4.4 CaseZ and CaseX.- 2.5 Functions and Tasks.- 2.5.1 Tasks.- 2.5.2 Functions.- 2.5.3 A Structural View.- 2.6 Summary.- 2.7 Exercises.- 3. Concurrent Process Statements.- 3.1 Concurrent Processes.- 3.2 Events.- 3.2.1 Event Control Statement.- 3.2.2 Named Events.- 3.2.3 An Example of Hierarchical Names.- 3.3 The Wait Statement.- 3.3.1 A Complete Producer-Consumer Handshake.- 3.3.2 Comparison of the Wait and While Statements.- 3.3.3 Comparison of Wait and Event Control Statements.- 3.4 Disabling Named Blocks.- 3.5 Quasi-continuous assignment.- 3.6 Sequential and Parallel Blocks.- 3.7 Exercises.- 4. Logic Level Modeling.- 4.1 Introduction.- 4.2 Logic Gates and Nets.- 4.2.1 Modeling Using Primitive Logic Gates.- 4.2.2 Four-Level Logic Values.- 4.2.3 Nets.- 4.2.4 Module Port Specifications.- 4.3 Continuous Assignment.- 4.3.1 Behavioral Modeling of Combinational Circuits.- 4.3.2 Net and Continuous Assign Declarations.- 4.4 Parameterized Definitions.- 4.5 Logic Delay Modeling.- 4.5.1 A Gate Level Modeling Example.- 4.5.2 Gate and Net Delays.- 4.5.3 Minimum, Typical, and Maximum Delays.- 4.6 Delay Paths Across a Module.- 4.7 Summary.- 4.8 Exercises.- 5. Defining Gate Level Primitives.- 5.1 Combinational Primitives.- 5.1.1 Basic Features of User-Defined Primitives.- 5.1.2 Describing Combinational Logic Circuits.- 5.2 Level- and Edge-Sensitive Sequential Primitives.- 5.2.1 Level-Sensitive Primitives.- 5.2.2 Edge-Sensitive Primitives.- 5.3 Shorthand Notation.- 5.4 Mixed Level- and Edge-Sensitive Primitives.- 5.5 Summary.- 5.6 Exercises.- 6. Switch Level Modeling.- 6.1 A Dynamic MOS Shift Register Example.- 6.2 Switch Level Modeling.- 6.2.1 Strength Modeling.- 6.2.2 Strength Definitions.- 6.2.3 An Example Using Strengths.- 6.2.4 Resistive MOS Gates.- 6.3 Ambiguous Strengths.- 6.3.1 Illustrations of Ambiguous Strengths.- 6.3.2 The Underlying Calculations.- 6.4 Summary.- 6.5 Exercises.- 7. Two Large Examples.- 7.1 The miniSim Example.- 7.1.1 Overview.- 7.1.2 The miniSim Source.- 7.1.3 Simulation Results.- 7.2 The 8251A Example.- 7.2.1 Overview.- 7.2.2 The 8251A Source.- 7.3 Exercises.- Appendix A. Lexical Conventions.- A.1 White Space and Comments.- A.2 Operators.- A.3 Numbers.- A.4 Strings.- A.5 Identifiers, System Names, and Keywords.- Appendix B. Verilog Operators.- B.1 Table of Operators.- B.2 Operator Precedence.- B.3 Operator Truth Tables.- B.3.1 Bitwise AND.- B.3.2 Bitwise OR.- B.3.3 Bitwise XOR.- B.3.4 Bitwise XNOR.- B.4 Expression Bit Lengths.- Appendix C. Verilog Gate Types.- C.1 Logic Gates.- C.2 BUF and NOT Gates.- C.3 BUFIF and NOTIF Gates.- C.4 MOS Gates.- C.5 Bidirectional Gates.- C.6 CMOS Gates.- C.7 Pullup and Pulldown Gates.- Appendix D. Registers, Memories, Integers, and Time.- D.1 Registers.- D.2 Memories.- D.3 Integers and Times.- Appendix E. System Tasks and Functions.- E.1 Display and Write Tasks.- E.2 Continuous Monitoring.- E.3 Strobed Monitoring.- E.4 File Output.- E.5 Simulation Time.- E.6 Stop and Finish.- E.7 Random.- Appendix F. Formal Syntax Definition.- F.1 Source Text.- F.2 Declarations.- F.3 Primitive Instances.- F.4 Module Instantiations.- F.5 Behavioral Statements.- F.6 Specify Section.- F.7 Expressions.- F.8 General.

Editorial Reviews

Fatbrain.com Review:

This classic Verilog (IEEE Std 1364-1995) hardware description reference text has been updated and expanded once again to meet the requirements of university courses. The authors have taken an example-oriented approach to introduce Verilog. They concentrate on design specification and avoid specific detail on simulator and synthesis. Thus, students should be able to write working executable models after studying this text, regardless of the simulator or synthesis tools they use.

Highlights:

• Authors Thomas and Moorby introduce behavioral modeling of combinational and clock sequenced circuits. They discuss a module hierarchy and detail a finite state machine datapath. They then delve into process modeling, concurrent processes and advanced timing models.
• During the modeling process students learn the constructs, statements and structure of Verilog with examples and discussions of if-then-else statements, multiway branching and continuous assignments.
• It also covers logic level modeling, logic and behavioral synthesis and switch level modeling.

Advantages:

• Includes open-ended projects for modeling power dissipation and a floppy disk controller.
• The appendices contain additional Verilog references, testbench modules, lexical conventions and formal syntax definitions.
• The CD-ROM includes a Verilog simulator, synthesis software (time limited) and examples from this publication.

Related Titles:

The following publications provide supplementary information: Verilog Digital Computer Design : Algorithms into Hardware, Digital Design and Synthesis with Verilog HDL and HDL Chip Design. The last publication is interesting. It contains Verilog and VHDL code for the same models, side by side, including different ways and options of modeling. It's primarily a modeling guide for ASIC and FPGAs.

A tutorial presentation of the Verilog language designed for engineers and students interested in describing, simulating and synthesizing digital systems. The included CD-ROM contains five versions of the Veri Well Verilog simulator for five different platforms: DOS, Windows, Macintosh, Linux and Sparc. The CD-Rom also includes examples from the book, which can be simulated and modified and re-simulated. The simulator can be used to solve the exercises at the end of each chapter. Annotation c. Book News, Inc., Portland, OR (booknews.com)

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