The drive towards increased packaging density relies on the stacking of die layers in multi-chip modules (MCMs). Extremely high integration density can be achieved with these modules. There are two fundamental methods for maximizing functional density in a MCM. Either the individual die or the entire packaged die layer can be thinned. In both cases, die thinning and packaging methods must be developed. A detailed process for thinning individual die to sub-35 mum is outlined. The process consists of pseudo-wafer lamination, lapping, chemical mechanical planarization (CMP), and die release. A pseudo-wafer is created by adhering die to a glass substrate. Mechanical lapping is used to remove the bulk silicon and reduce die thickness to approximately 50 mum. CMP is used to attain thicknesses of sub-35 mum and remove the silicon damage layer. This process can reliably produce die thinned to sub-35 mum with +/- 1.5 mum total thickness variation (TTV) and good surface characteristics. The die are released from the glass substrate and encapsulated in a dielectric material. Multiple die layers can be stacked to form a MCM. For packaged layer thinning, a method is developed to encapsulate thick die in a dielectric material on a cavity wafer. Frontside processing creates multiple layers of interconnects. The encapsulated die layer is thinned to approximately 75 mum and backside processing is performed. These layers are subsequently bonded and interconnected to create the MCM.