Timing Optimization Through Clock Skew Scheduling

by Ivan S. Kourtev, Baris Taskin, Eby G. Friedman

Overview

The focus of this book is on timing analysis and optimization techniques for circuits with level-sensitive memory elements (registers). Level-sensitive registers are becoming significantly more popular in practice as integrated circuit densities are increasing and the 'performance-per-power' metric for integrated circuits becomes a key issue. Therefore, techniques for understanding level-sensitive based circuits and for optimizing the performance of such circuits are increasingly important. The book contains a linear programming formulation applicable to the timing analysis of large scale circuits. It includes a delay insertion methodology, and offers an overview of circuit partitioning, placement, and synchronization methodologies that enables the implementation of high speed, low power circuits synchronized with ultra-modern resonant clocking technology.

Product Details

ISBN-13:	9781441943774
Publisher:	Springer US
Publication date:	11/04/2010
Edition description:	Softcover reprint of hardcover 1st ed. 2009
Pages:	266
Product dimensions:	6.10(w) x 9.25(h) x 0.24(d)

Table of Contents

List of Tables

Preface

1: Introduction

2: VLSI Systems

3: Signal Delay in VLSI Systems

4: Timing Properties of Synchronous Systems

5: Clock Scheduling and Clock Tree Synthesis

6: Clock Scheduling for Improved Reliability

7: Practical Considerations

8: Experimental Results

9: Conclusions

10: Future Directions

References

Appendices

Index

About the Authors