Tradeoffs and Optimization in Analog CMOS Design / Edition 1

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Overview

Analog CMOS integrated circuits are in widespread use for communications, entertainment, multimedia, biomedical, and many other applications that interface with the physical world. Although analog CMOS design is greatly complicated by the design choices of drain current, channel width, and channel length present for every MOS device in a circuit, these design choices afford significant opportunities for optimizing circuit performance.

This book addresses tradeoffs and optimization of device and circuit performance for selections of the drain current, inversion coefficient, and channel length, where channel width is implicitly considered. The inversion coefficient is used as a technology independent measure of MOS inversion that permits design freely in weak, moderate, and strong inversion. 

This book details the significant performance tradeoffs available in analog CMOS design and guides the designer towards optimum design by describing:

  • An interpretation of MOS modeling for the analog designer, motivated by the EKV MOS model, using tabulated hand expressions and figures that give performance and tradeoffs for the design choices of drain current, inversion coefficient, and channel length; performance includes effective gate-source bias and drain-source saturation voltages, transconductance efficiency, transconductance distortion, normalized drain-source conductance, capacitances, gain and bandwidth measures, thermal and flicker noise, mismatch, and gate and drain leakage current
  • Measured data that validates the inclusion of important small-geometry effects like velocity saturation, vertical-field mobility reduction, drain-induced barrier lowering, and inversion-level increases in gate-referred, flicker noise voltage
  • In-depth treatment of moderate inversion, which offers low bias compliance voltages, high transconductance efficiency, and good immunity to velocity saturation effects for circuits designed in modern, low-voltage processes
  • Fabricated design examples that include operational transconductance amplifiers optimized for various tradeoffs in DC and AC performance, and micropower, low-noise preamplifiers optimized for minimum thermal and flicker noise
  • A design spreadsheet, available at the book web site, that facilitates rapid, optimum design of MOS devices and circuits 

Tradeoffs and Optimization in Analog CMOS Design is the first book dedicated to this important topic. It will help practicing analog circuit designers and advanced students of electrical engineering build design intuition, rapidly optimize circuit performance during initial design, and minimize trial-and-error circuit simulations. 

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Product Details

  • ISBN-13: 9780470031360
  • Publisher: Wiley, John & Sons, Incorporated
  • Publication date: 8/25/2008
  • Edition number: 1
  • Pages: 632
  • Product dimensions: 6.90 (w) x 9.90 (h) x 1.60 (d)

Meet the Author

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Table of Contents

List of Symbols and Abbreviations

1 Introduction 1

1.1 Importance of Tradeoffs and Optimization in Analog CMOS Design 1

1.2 Industry Designers and University Students as Readers 2

1.3 Organization and Overview of Book 3

1.4 Full or Selective Reading of Book 5

1.5 Example Technologies and Technology Extensions 6

1.6 Limitations of the Methods 6

1.7 Disclaimer 7

Pt. I MOS Device Performance, Tradeoffs and Optimization for Analog CMOS Design 9

2 MOS Design from Weak through Strong Inversion 11

2.1 Introduction 11

2.2 MOS Design Complexity Compared to Bipolar Design 12

2.3 Bipolar Transistor Collector Current and Transconductance 12

2.4 MOS Drain Current and Transconductance 13

2.5 MOS Drain-Source Conductance 23

2.6 Analog CMOS Electronic Design Automation Tools and Design Methods 25

References 30

3 MOS Performance versus Drain Current, Inversion Coefficient, and Channel Length 33

3.1 Introduction 33

3.2 Advantages of Selecting Drain Current, Inversion Coefficient, and Channel Length in Analog CMOS Design 34

3.3 Process Parameters for Example Processes 40

3.4 Substrate Factor and Inversion Coefficient 46

3.5 Temperature Effects 55

3.6 Sizing Relationships 61

3.7 Drain Current and Bias Voltages 67

3.8 Small-Signal Parameters and Intrinsic Voltage Gain 98

3.9 Capacitances and Bandwidth 169

3.10 Noise 188

3.11 Mismatch 233

3.12 Leakage Current 268

References 283

4 Tradeoffs in MOS Performance, and Design of Differential Pairs and Current Mirrors 295

4.1 Introduction 295

4.2 Performance Trends 296

4.3 Performance Tradeoffs 303

4.4 Design of Differential Pairs and Current Mirrors Using the Analog CMOS Design, Tradeoffs andOptimization Spreadsheet 346

References 373

Pt. II Circuit Design Examples Illustrating Optimization for Analog CMOS Design 375

5 Design of CMOS Operational Transconductance Amplifiers Optimized for DC, Balanced, and AC Performance 377

5.1 Introduction 377

5.2 Circuit Description 379

5.3 Circuit Analysis and Performance Optimization 382

5.4 Design Optimization and Resulting Performance for the Simple OTAs 425

5.5 Design Optimization and Resulting Performance for the Cascoded OTAs 448

5.6 Prediction Accuracy for Design Guidance and Optimization 474

References 476

6 Design of Micropower CMOS Preamplifiers Optimized for Low Thermal and Flicker Noise 477

6.1 Introduction 477

6.2 Using the Lateral Bipolar Transistor for Low-Flicker-Noise Applications 478

6.3 Measures of Preamplifier Noise Performance 479

6.4 Reported Micropower, Low-Noise CMOS Preamplifiers 483

6.5 MOS Noise versus the Bias Compliance Voltage 486

6.6 Extraction of MOS Flicker-Noise Parameters 504

6.7 Differential Input Preamplifier 507

6.8 Single-Ended Input Preamplifier 531

6.9 Prediction Accuracy for Design Guidance and Optimization 549

References 552

7 Extending Optimization Methods to Smaller-Geometry CMOS Processes and Future Technologies 555

7.1 Introduction 555

7.2 Using the Inversion Coefficient for CMOS Process Independence and for Extension to Smaller-Geometry Processes 556

7.3 Enhancing Optimization Methods by Including Gate Leakage Current Effects 560

7.4 Using an Inversion Coefficient Measure for Non-CMOS Technologies 561

References 562

App The Analog CMOS Design, Tradeoffs and Optimization Spreadsheet 565

Index 583

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