Tradeoffs and Optimization in Analog CMOS Design / Edition 1

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Analog CMOS integrated circuits are in widespread use forcommunications, entertainment, multimedia, biomedical, and manyother applications that interface with the physical world. Althoughanalog CMOS design is greatly complicated by the design choices ofdrain current, channel width, and channel length present for everyMOS device in a circuit, these design choices afford significantopportunities for optimizing circuit performance.

This book addresses tradeoffs and optimization of device andcircuit performance for selections of the drain current, inversioncoefficient, and channel length, where channel width is implicitlyconsidered. The inversion coefficient is used as a technologyindependent measure of MOS inversion that permits design freely inweak, moderate, and strong inversion. 

This book details the significant performance tradeoffsavailable in analog CMOS design and guides the designer towardsoptimum design by describing:

  • An interpretation of MOS modeling for the analog designer,motivated by the EKV MOS model, using tabulated hand expressionsand figures that give performance and tradeoffs for the designchoices of drain current, inversion coefficient, and channellength; performance includes effective gate-source bias anddrain-source saturation voltages, transconductance efficiency,transconductance distortion, normalized drain-source conductance,capacitances, gain and bandwidth measures, thermal and flickernoise, mismatch, and gate and drain leakage current
  • Measured data that validates the inclusion of importantsmall-geometry effects like velocity saturation, vertical-fieldmobility reduction, drain-induced barrier lowering, andinversion-level increases in gate-referred, flicker noisevoltage
  • In-depth treatment of moderate inversion, which offers low biascompliance voltages, high transconductance efficiency, and goodimmunity to velocity saturation effects for circuits designed inmodern, low-voltage processes
  • Fabricated design examples that include operationaltransconductance amplifiers optimized for various tradeoffs in DCand AC performance, and micropower, low-noise preamplifiersoptimized for minimum thermal and flicker noise
  • A design spreadsheet, available at the book web site, thatfacilitates rapid, optimum design of MOS devices andcircuits 

Tradeoffs and Optimization in Analog CMOS Design is thefirst book dedicated to this important topic. It will helppracticing analog circuit designers and advanced students ofelectrical engineering build design intuition, rapidly optimizecircuit performance during initial design, and minimizetrial-and-error circuit simulations. 

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Product Details

  • ISBN-13: 9780470031360
  • Publisher: Wiley
  • Publication date: 8/25/2008
  • Edition number: 1
  • Pages: 632
  • Product dimensions: 6.90 (w) x 9.90 (h) x 1.60 (d)

Table of Contents




List of Symbols and Abbreviations.

1 Introduction.

1.1 Importance of Tradeoffs and Optimization in Analog CMOSDesign.

1.2 Industry Designers and University Students as Readers.

1.3 Organization and Overview of Book.

1.4 Full or Selective Reading of Book.

1.5 Example Technologies and Technology Extensions.

1.6 Limitations of the Methods.

1.7 Disclaimer.

PART I MOS Device Performance, Tradeoffs and Optimization forAnalog CMOS Design.

2 MOS Design from Weak through Strong Inversion.

2.1 Introduction.

2.2 MOS Design Complexity Compared to Bipolar Design.

2.3 Bipolar Transistor Collector Current andTransconductance.

2.4 MOS Drain Current and Transconductance.

2.5 MOS Drain–Source Conductance.

2.6 Analog CMOS Electronic Design Automation Tools and DesignMethods.


3 MOS Performance versus Drain Current, InversionCoefficient, and Channel Length.

3.1 Introduction.

3.2 Advantages of Selecting Drain Current, InversionCoefficient, and Channel Length in Analog CMOS Design.

3.3 Process Parameters for Example Processes.

3.4 Substrate Factor and Inversion Coefficient.

3.5 Temperature Effects.

3.6 Sizing Relationships.

3.7 Drain Current and Bias Voltages.

3.8 Small-Signal Parameters and Intrinsic Voltage Gain.

3.9 Capacitances and Bandwidth.

3.10 Noise.

3.11 Mismatch.

3.12 Leakage Current.


4 Tradeoffs in MOS Performance, and Design of DifferentialPairs and Current Mirrors.

4.1 Introduction.

4.2 Performance Trends.

4.3 Performance Tradeoffs.

4.4 Design of Differential Pairs and Current Mirrors Using theAnalog CMOS Design, Tradeoffs and OptimizationSpreadsheet.


PART II Circuit Design Examples Illustrating Optimization forAnalog CMOS Design.

5 Design of CMOS Operational Transconductance AmplifiersOptimized for DC, Balanced, and AC Performance.

5.1 Introduction.

5.2 Circuit Description.

5.3 Circuit Analysis and Performance Optimization.

5.4 Design Optimization and Resulting Performance for the SimpleOTAs.

5.5 Design Optimization and Resulting Performance for theCascoded OTAs.

5.6 Prediction Accuracy for Design Guidance andOptimization.


6 Design of Micropower CMOS Preamplifiers Optimized for LowThermal and Flicker Noise.

6.1 Introduction.

6.2 Using the Lateral Bipolar Transistor for Low-Flicker-NoiseApplications.

6.3 Measures of Preamplifier Noise Performance.

6.4 Reported Micropower, Low-Noise CMOS Preamplifiers.

6.5 MOS Noise versus the Bias Compliance Voltage.

6.6 Extraction of MOS Flicker-Noise Parameters.

6.7 Differential Input Preamplifier.

6.8 Single-Ended Input Preamplifier.

6.9 Prediction Accuracy for Design Guidance andOptimization.

6.10 Summary of Low-Noise Design Methods and ResultingChallenges in Low-Voltage Processes.


7 Extending Optimization Methods to Smaller-Geometry CMOSProcesses and Future Technologies.

7.1 Introduction.

7.2 Using the Inversion Coefficient for CMOS ProcessIndependence and for Extension to Smaller-Geometry Processes.

7.3 Enhancing Optimization Methods by Including Gate LeakageCurrent Effects.

7.4 Using an Inversion Coefficient Measure for Non-CMOSTechnologies.


Appendix: The Analog CMOS Design, Tradeoffs andOptimization Spreadsheet.


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