ULSI Semiconductor Technology Atlas
More than 1,100 TEM images illustrate the science of ULSI

The natural outgrowth of VLSI (Very Large Scale Integration), Ultra Large Scale Integration (ULSI) refers to semiconductor chips with more than 10 million devices per chip. Written by three renowned pioneers in their field, ULSI Semiconductor Technology Atlas uses examples and TEM (Transmission Electron Microscopy) micrographs to explain and illustrate ULSI process technologies and their associated problems.

The first book available on the subject to be illustrated using TEM images, ULSI Semiconductor Technology Atlas is logically divided into four parts:
* Part I includes basic introductions to the ULSI process, device construction analysis, and TEM sample preparation
* Part II focuses on key ULSI modules—ion implantation and defects, dielectrics and isolation structures, silicides/salicides, and metallization
* Part III examines integrated devices, including complete planar DRAM, stacked cell DRAM, and trench cell DRAM, as well as SRAM as examples for process integration and development
* Part IV emphasizes special applications, including TEM in advanced failure analysis, TEM in advanced packaging development and UBM (Under Bump Metallization) studies, and high-resolution TEM in microelectronics


This innovative guide also provides engineers and managers in the microelectronics industry, as well as graduate students, with:
* More than 1,100 TEM images to illustrate the science of ULSI
* A historical introduction to the technology as well as coverage of the evolution of basic ULSI process problems and issues
* Discussion of TEM in other advanced microelectronics devices and materials, such as flash memories, SOI, SiGe devices, MEMS, and CD-ROMs
1100681455
ULSI Semiconductor Technology Atlas
More than 1,100 TEM images illustrate the science of ULSI

The natural outgrowth of VLSI (Very Large Scale Integration), Ultra Large Scale Integration (ULSI) refers to semiconductor chips with more than 10 million devices per chip. Written by three renowned pioneers in their field, ULSI Semiconductor Technology Atlas uses examples and TEM (Transmission Electron Microscopy) micrographs to explain and illustrate ULSI process technologies and their associated problems.

The first book available on the subject to be illustrated using TEM images, ULSI Semiconductor Technology Atlas is logically divided into four parts:
* Part I includes basic introductions to the ULSI process, device construction analysis, and TEM sample preparation
* Part II focuses on key ULSI modules—ion implantation and defects, dielectrics and isolation structures, silicides/salicides, and metallization
* Part III examines integrated devices, including complete planar DRAM, stacked cell DRAM, and trench cell DRAM, as well as SRAM as examples for process integration and development
* Part IV emphasizes special applications, including TEM in advanced failure analysis, TEM in advanced packaging development and UBM (Under Bump Metallization) studies, and high-resolution TEM in microelectronics


This innovative guide also provides engineers and managers in the microelectronics industry, as well as graduate students, with:
* More than 1,100 TEM images to illustrate the science of ULSI
* A historical introduction to the technology as well as coverage of the evolution of basic ULSI process problems and issues
* Discussion of TEM in other advanced microelectronics devices and materials, such as flash memories, SOI, SiGe devices, MEMS, and CD-ROMs
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ULSI Semiconductor Technology Atlas

ULSI Semiconductor Technology Atlas

ULSI Semiconductor Technology Atlas

ULSI Semiconductor Technology Atlas

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Overview

More than 1,100 TEM images illustrate the science of ULSI

The natural outgrowth of VLSI (Very Large Scale Integration), Ultra Large Scale Integration (ULSI) refers to semiconductor chips with more than 10 million devices per chip. Written by three renowned pioneers in their field, ULSI Semiconductor Technology Atlas uses examples and TEM (Transmission Electron Microscopy) micrographs to explain and illustrate ULSI process technologies and their associated problems.

The first book available on the subject to be illustrated using TEM images, ULSI Semiconductor Technology Atlas is logically divided into four parts:
* Part I includes basic introductions to the ULSI process, device construction analysis, and TEM sample preparation
* Part II focuses on key ULSI modules—ion implantation and defects, dielectrics and isolation structures, silicides/salicides, and metallization
* Part III examines integrated devices, including complete planar DRAM, stacked cell DRAM, and trench cell DRAM, as well as SRAM as examples for process integration and development
* Part IV emphasizes special applications, including TEM in advanced failure analysis, TEM in advanced packaging development and UBM (Under Bump Metallization) studies, and high-resolution TEM in microelectronics


This innovative guide also provides engineers and managers in the microelectronics industry, as well as graduate students, with:
* More than 1,100 TEM images to illustrate the science of ULSI
* A historical introduction to the technology as well as coverage of the evolution of basic ULSI process problems and issues
* Discussion of TEM in other advanced microelectronics devices and materials, such as flash memories, SOI, SiGe devices, MEMS, and CD-ROMs

Product Details

ISBN-13: 9780471457725
Publisher: Wiley
Publication date: 10/06/2003
Pages: 680
Product dimensions: 7.24(w) x 10.24(h) x 1.46(d)

About the Author

CHIH-HANG TUNG is a senior member of the technical staff and Project Leader at the Institute of Microelectronics in Singapore.

GEORGE T. T. SHENG was the first to develop cross-sectioning samples of TEM studies of semiconductor devices and has been involved with many other groundbreaking projects at Bell Labs.

CHIH-YUAN LU is Chairman and CEO of Ardentec Corp., an ULSI testing service company. He is also CTO of Macronix International Co., Ltd., the eighth largest worldwide NVM semiconductor company.

Read an Excerpt

ULSI Semiconductor Technology Atlas


By Chih-Hang Tung George T. T. Sheng Chih-Yuan Lu

John Wiley & Sons

Copyright © 2003 John Wiley & Sons, Inc.
All right reserved.

ISBN: 0-471-45772-8


Chapter One

Microelectronics and Microscopy

The first transistor was invented by John Bardeen, Walter Brattain, and William Shockley on December 16, 1947, at Bell Labs (Early 2001). A photograph of this early transistor is shown in Fig. 1.1. The three men shared the Nobel Prize for their invention in 1956. In about 10 years time, on September 12, 1958, Jack St. Clair Kilby of Texas Instruments, demonstrated the first integrated circuit on a tiny piece of germanium with protruding wires glued to a glass slide, as shown in Fig. 1.2. It was a phase-shift oscillator, which was a favorite demonstration vehicle for linear circuits at that time. As power was applied, it oscillated at 1.3 megacycles (Wagner 2001). The invention brought a Nobel Prize in physics to Kilby in 2000.

The most remarkable aspect of the integrated circuit was the cost reduction that occurred over the 40 years following its invention. In 1958, a single silicon transistor sold for about $10. Today, $10 will buy over 20 million transistors, an equal number of passive components, and all of the interconnections that make them a useful memory chip. The field of integrated circuits has produced such dramatic advances over the past 40 years that revolutionarydevelopments have become commonplace. Since the early 1970s, technical progress has propelled the industry from small scale integration (SSI, fewer than 30 devices on a chip), to medium scale integration (MSI, 30 to [10.sup.3] devices on a chip), to large-scale integration (LSI, [10.sup.3] to [10.sup.5] devices on a chip), to very large scale integration (VLSI, [10.sup.5] to [10.sup.7] devices on a chip), and now to ultra large scale integration (ULSI, more than [10.sup.7] devices on a chip). The designer of an electronic system seeks to maximize four product features: reliability, economy, performance, and functional density. The way to do this has been to observe four minimization principles, the so-called Kilby principles (Warner 2001): minimize the number of parts in the system, the number of different materials in the system, the number of process steps required to fabricate the system, and the differences among these process steps.

As miniaturization continues, inevitably more new materials will be in use. Beside the traditional silicon oxide and nitride dielectrics, we have now low-[kappa] dielectrics that incorporate a whole range of polymer materials. We have high-[kappa] dielectrics that use a wide range of metal oxides. In metallization the same transformation occurs when polysilicon, titanium and tantalum nitrides, tungsten and refractory alloys, various silicides, aluminum alloys and copper alloys are used. The list is growing as new interconnect challenges emerge. Over the years the Kilby principles have demonstrated their validity with dramatic improvements in all four of the desirable system properties he cited. The crucial point in the development of modern microelectronics was the joining-integration-of individual resistors, capacitors, and transistors on the surface of the semiconductor substrate (Warner 2001; J. M. Early 2001; Wagner 2001). A solid state integrated circuit (IC) is thus born. What is surprising is that this happened about 40 years ago. Once the first solid state integrated device was made, the shrinking, or miniaturization, proceeded exponentially. The reader interested in this amazing history is encouraged to consult the following articles:

R. M. Warner, "Microelectronics: Its Unusual Origin and Personality," IEEE Transactions on Electron Devices 48 (11), 2457-2467, 2001.

50 Years of Electron Devices, The IEEE Electron Devices Society and Its Technologies, 1952-2002. Foreword by Cary Yang, IEEE, 2002.

J. M. Early, "Out of Murray Hill to Play: An Early History of Transistors," IEEE Transactions on Electron Devices 48 (11), 2468-2472, 2001.

B. Brar, G. J. Sullivan, and P. M. Asbeck, "Herb's Bipolar Transistor," IEEE Transactions on Electron Devices 48 (11), 2473-2476, 2001.

1.1 MICROELECTRONICS AND MICROSCOPY

In the microelectronics industry there is a need to observe, analyze, and identify a product's characteristics not only to ascertain why and how devices work but, more important, why they fail. Apart from electrical parameters, knowledge of the device's physical structure and constituent chemistry is vital to understanding the process. Device analysis is becoming more critical as all aspects of the technology are pushed toward their fundamental limits. Increasingly more precision is required as more emphasis is placed on the purity of the starting materials, the uniformity of thin films, the quality of the interface, and the performance of Si-substrate materials. As a result more cross-disciplinary engineers and researchers are becoming involved in the semiconductor process characterization and failure analyses (Richards and Footner 1992).

The advances in metrology and analytical work in microelectronics devices can be divided chronologically into three historical developments: early optical microscopy (OM), scanning electron microscopy (SEM), and presently transmission electron microscopy (TEM) stage. Over the years as dimensions shrank yet more, new questions would arise about configurations in the third dimension that would tax the capability of even the scanning electron microscope. As narrow line-widths and spaces were observed to have a leverage effect on edges and other vertical dimensions, the need for high-resolution microscopy of the vertical cross section through devices led to the development of using transmission electron microscopy in ULSI device analysis.

There are a great many analytical tools that are thus widely used in microelectronics and ULSI process characterization and failure analyses. Basically they can be categorized by the incident and emitted particles that they employ, as listed in Table 1.1. Different techniques have different capabilities and limitations. Table 1.2 shows the resolution, sensitivity, and limitations for some of the frequently used analytical techniques in microelectronics.

Tables 1.1 and 1.2 are not exhaustive; they show where TEM fits within a range of techniques and the use of the electron beam in TEM for probes and detection of sample structures. There is no single analytical technique that is capable of fulfilling all the analytical needs for the modern microelectronics industry, however. Often traditional techniques are improved and modified to meet each new challenge and mission in ULSI process characterization. Almost yearly the International Technology Roadmap for Semiconductors (ITRS) is updated and revised on the metrology needs of ULSI process analysis. Most of the technologies mentioned in Tables 1.1 and 1.2 were on the roadmap at one time or another. As ULSI technology advances, the emerging technologies will be developed to fill new needs (Diebold 2000).

All of the technologies mentioned here are available commercially, as are the numerous reference books cited. The interested reader should consult these for more detailed information. Below we give acronyms of the techniques mentioned in this section, in alphabetical order:

AES Auger electron spectroscopy

AFM Atomic force microscopy

EDX Energy dispersive X-ray spectroscopy

EELS Electron energy loss spectroscopy

FTIR Fourier transform infrared spectroscopy

GCMS Gas chromatography-mass spectrometry

ISS Ion scattering spectroscopy

LEED Low energy electron diffraction

LIMA Laser ionization mass analysis

PIXE Proton-induced X-ray emission

RBS Rutherford backscattering spectrometry

RHEED Reflection high-energy electron diffraction

SEM Scanning electron microscopy

SIMS Secondary ion mass spectrometry

SPM Scanning probe microscopy

TEM Transmission electron microscopy

TOF Time of flight (SIMS)

TXRF Total reflection X-ray fluorescence

UPS Ultraviolet photoelectron spectroscopy

XPS X-ray photoelectron spectroscopy (also called ESCA)

XRD X-ray diffraction

We will selectively, and briefly, discuss only a few of the more common techniques in this chapter.

1.2 OPTICAL MICROSCOPY AND RELATED TECHNIQUES

The primary, and preliminary, tool for all analyses, whether it be basic process characterization or defect and failure analysis, is optical microscopy (OM). The optical microscope is inexpensive and easy to use, and it requires little operational training. It is a logical extension of initial observation by the unaided eye. Optical microscopy is a technique that uses an illumination source to enlarge an image within the optical range. The following discussion covers the most popular optical microscopes: light microscopes, IR microscopes, emission microscopes, and laser confocal microscopes.

Light Microscopy

Optical microscopes have a ubiquitous presence in modern microelectronics laboratories. Several different light microscopes are widely used in today's analysis work. A low-power (usually 5-100x) binocular stereomicroscope can provide an image of high quality and full-depth perception. The considerable depth of field inherent in this instruments together with a continuous zoom system, allows for a full examination of the external and internal features of the package of an electronics device, as demonstrated in Fig. 1.3. Long working distance, large depth of focus, and the capability to tilt and view are advantageous in field work, and these features are available in most modern commercial microscopes. However, a full examination of the device requires the use of a more sophisticated light microscope that permits examination at magnifications from 5x up to 2000x, as seen in Fig. 1.4. Details of the device's circuit layout can be fully traced by a light microscope when there is only one metal layer interconnection. A metallography type microscope uses an incident light source in the visible spectrum range. The incident light (source) and the reflected (image) light are usually on the same optical axis in the microscope. The bright field reflection mode technique, which is extensively used in metallography, has the advantage for enabling examination of a device's surface without much effort in preparing the sample. Since polychromatic light is usually used to illuminate the sample, information can be obtained from the colors, as this is invaluable in the assessment of characteristics such as the thickness and integrity of the oxide layer. The colors associated with a range of oxide thicknesses have been well studied and tabulated (Richards and Footner 1992). The problems with the light microscope are that the image often lacks contrast can further be degraded by the presence of a glare (due to diffuse nonspecular reflections from the object's surface). A more sophisticated light microscope with modifications to the incident illuminators allows the use of dark field, phase contrast, polarized light, and Nomarski interference techniques, all of which can be applied in microelectronics analysis.

For example, the use of dark field illumination has the advantage of imaging only the nonplanar surface features of a device, so features such as step edges and surface roughness stand out in the dark field imaging mode. Another optical microscope technique that is used in device examination is Nomarski differential interference contrast. In this mode the device is illuminated by a plane-polarized light that is separated into two beams by a Wollaston prism. One of the beams passes through the feature of interest, and the other to one side. When the beams are recombined by a second prism above the objective lens, the phase change introduced into the object beam by the presence of specimen is converted into an amplitude of color difference. The image contrast is enhanced at slightly different surface levels, thus bestowing the capability of imaging surface features of only a few tens of nanometers in height. In device analyses the Nomarski technique is valuable for two reasons. First, it can be used to image the slight variations in thickness of thermally grown oxides in regions of different doping. When the oxides are removed, small steps left are on the surface, and these are imaged in strong contrast under Nomarski conditions, as shown in Fig. 1.5. Thus it is possible to identify optically the layout of device diffusions by this technique. Second, the Nomarski technique's sensitivity to very small surface aspirates makes it useful in the detection and location of etch pits and other surface defects. This is particularly useful in process optimization and defect detection. Often, however, etch pits and very shallow epitaxial growth features cannot be detected even by the SEM.

There are many disadvantages of light microscopy besides its limited spatial resolution:

It often lacks contrast and often degraded by the presence of glare.

It is restricted to surface examination, and

It has limited depth of focus at high magnification.

In the use of the light microscope to retrieve circuit information from modern devices, two major issues have arisen:

1. The spatial resolution is insufficient. Figure 1.6 shows an image of a 0.5 µm VLSI technology device as seen using an optical microscope. Several distinctive areas (or blocks) can be distinguished, and with some experience, the functions of some of the blocks can be identified. But observation of further detail with the optical microscope is nearly impossible.

2. Besides the inadequate resolution power, another problem in using the light microscope is the presence of multiple layers of interconnection in modern devices. For this reason the transistor, which has multilayer interconnections is rarely observed under a light microscope. Figure 1.7a shows the multilayer interconnections in a high-magnification optical image. The circuit information can no longer be retrieved. Figure 1.7b shows at lower magnification that most of the time the upper metals are ground and power supplies. They are often wide, so they cover most of the area.

Infrared Microscopy and Emission Microscope

The advantage of using infrared (wavelength 80-130 nm) as the illumination source in studying microelectronics devices is that silicon becomes essentially transparent at this wavelength range. A microscope using special IR transmitting optics and an IR camera and detector can readily be employed to investigate the interior of the device. This technique has particular application in flip-chip packaging, which should soon become the dominant packaging technology in modern high-pin-count devices.

Continues...


Excerpted from ULSI Semiconductor Technology Atlas by Chih-Hang Tung George T. T. Sheng Chih-Yuan Lu Copyright © 2003 by John Wiley & Sons, Inc.. Excerpted by permission.
All rights reserved. No part of this excerpt may be reproduced or reprinted without permission in writing from the publisher.
Excerpts are provided by Dial-A-Book Inc. solely for the personal use of visitors to this web site.

Table of Contents

FOREWORD ix

PREFACE xi

PART I 1

1 Microelectronics and Microscopy 3

2 ULSI Process Technology 36

3 Applications of TEM for Construction Analysis 61

4 TEM Sample Preparation Techniques 90

PART II 141

5 Ion Implantation and Substrate Defects 143

6 Dielectrics and Isolation 179

7 Silicides, Polycide, and Salicide 256

8 Metallization and Interconnects 287

PART III 343

9 ULSI Devices I: DRAM Cell with Planar Capacitor 345

10 ULSI Devices II: DRAM Cell with Stacked Capacitor 365

11 ULSI Devices III: DRAM Cell with Trench Capacitor 399

12 ULSI Devices IV: SRAM 445

PART IV 475

13 TEM in Failure Analysis 477

14 Novel Devices and Materials 526

15 TEM in Under Bump Metallization (UBM) and Advanced Electronics Packaging Technologies 558

16 High-Resolution TEM in Microelectronics 609

INDEX 647

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From the Publisher

"...provides a historical introduction to the technology as well as coverage of the evolution of basic ULSI process problems and issue." (IEEE Solid-State Circuits Society Newsletter, January 2004)

"…strongly recommended…" (E-Streams, Vol. 7, No. 4)

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