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Overview

Universal Serial Bus System Architecture, Second Edition, based on the 2.0 version of the Universal Serial Bus specification, provides in-depth coverage and a detailed discussion of USB. It focuses on the USB protocol, signaling environment, and electrical specifications, along with the hardware/software interaction required to configure and access USB devices. Key topics include:

  • Hot plug support (detection of low-, full-, and high-speed devices)
  • Electrical signaling at the 1.5, 12, and 480Mb/s rates
  • 2.0 hub operation (including split transaction support)
  • 2.0 high-speed protocol (including high-bandwidth and ping transactions)
  • High-speed transceiver test modes
  • Suspend/resume operations
  • Device descriptors
  • Device requests (commands)
  • USB transaction protocols (low-, full-, and high-speed)
  • Bus-powered devices
  • Self-powered devices
  • Error detection and handling
  • Device configuration
  • Device classes

This second edition has been updated to reflect the changes in the USB specification from the original 1.0 to the current 2.0. The USB 2.0 specification defines high-speed transactions operating at 480Mb/s that increase throughput by a factor of 40 over the older USB devices. New high-bandwidth, ping, and split transactions have also been added to further increase efficiency of the high-speed protocol. The USB 2.0 specification makes major improvements to USB, while maintaining backward compatibility with 1.0 and 1.1 USB devices. If you design or test hardware or software that involves USB, you wouldn't want to miss the important updates in this book. Universal Serial Bus SystemArchitecture, Second Edition, is an essential, time-saving tool.

The accompanying CD-ROM includes an 85-minute USB 2.0 overview video by Don Anderson, featuring an introduction to the basic concepts underlying USB 2.0 bus operation and protocol. Topics covered include terminology, design goals of USB, a review of low- and full-speed operation used by USB 1.0 and 1.1 systems and devices, an introduction to USB 2.0 high-speed transfers, and how USB 2.0 hubs use split transactions to provide backward compatibility to low- and full-speed devices.

The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title is designed to illustrate the relationship between the software and hardware and explains thoroughly the architecture, features, and operations of systems built using one particular type of chip or hardware specification.

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Product Details

  • ISBN-13: 9780201309751
  • Publisher: Addison-Wesley
  • Publication date: 4/3/2001
  • Series: PC System Architecture Series
  • Edition description: REV
  • Edition number: 2
  • Pages: 544
  • Sales rank: 1,103,425
  • Product dimensions: 7.30 (w) x 9.25 (h) x 1.16 (d)

Meet the Author

MindShare, Inc. is one of the leading technical training companies in the hardware industry, providing innovative courses for dozens of companies, including Intel, IBM, and Compaq.

Don Anderson is the author of many MindShare books. He passes on his wealth of experience in digital electronics and computer design by training engineers, programmers, and technicians for MindShare.



0201309750AB07142003
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Read an Excerpt

PREFACE:

The MindShare Architecture Series

The MindShare Architecture book series includes: ISA System Architecture, EISA System Architecture, 80486 System Architecture, PCI System Architecture, Pentium System Architecture, PCMCIA System Architecture, PowerPC System Architecture, Plug-and-Play System Architecture, CardBus System Architecture, Protected Mode Software Architecture, Pentium Pro and Pentium II System Architecture, USB System Architecture, FireWire System Architecture, PCI-X System Architecture, and AGP System Architecture. The book series is published by Addison-Wesley.

Rather than duplicating common information in each book, the series uses the building-block approach. ISA System Architecture is the core book upon which the others build. Table 1 on page 1 illustrates the relationship of the books to each other.

Cautionary Note

The reader should keep in mind that MindShare's book series often deals with rapidly-evolving technologies. This being the case, it should be recognized that the book is a "snapshot" of the state of the targeted technology at the time that the book was completed. We attempt to update each book on a timely basis to reflect changes in the targeted technology, but, due to various factors (waiting for the next version of the spec to be "frozen," the time necessary to make the changes, and the time to produce the books and get them out to the distribution channels), there will always be a delay.

Specifications This Book is Based On

This book is based on the Universal Serial Bus 2.0 specification.

Organization of This Book

The book is divided into six partsand contains the chapters listed below:

Part I: Overview of USB 2.0

Chapter 1: This chapter provides an overview of the primary concepts of USB transfers and describes the interaction between USB system software, system hardware, and USB devices for USB 1.x systems and USB 2.0 system. The USB communications process is described, including the concept of the device framework. Each hardware and software element in a USB system is introduced and its primary functions are described.

Chapter 2: This chapter provides an overview of the primary concepts of USB transfers and describes the interaction between USB system software, system hardware, and USB devices for USB 1.x systems and USB 2.0 system. The USB communications process is described, including the concept of the device framework. Each hardware and software element in a USB system is introduced and its primary functions are described.

Chapter 3: USB defines a single connector type for attaching all USB peripherals to the host system. This chapter introduces the physical aspects of USB connectors and cables.

Chapter 4: This chapter discusses USB power distribution, along with issues related to bus powered devices and the operation of self-powered devices. The chapter also discusses the role of host software in detecting and reporting power related problems.

Part II: The USB Solution

Chapter 5: USB employs NRZI encoding and differential signaling to transfer information across USB cables. This chapter discusses the low- and full-speed signaling environment, including the differential signaling and NRZI encoding techniques used by the USB. The signaling environment must also support a wide range of other signal-related functions such as: detecting device attachment and removal, suspending and resuming operation, resetting a device, and others all of which are discussed in this chapter.

Chapter 6: USB supports four transfer types: interrupt, bulk, isochronous, and control. These transfer types and the process used to initiate and perform them are described in this chapter.

Chapter 7: Every transfer broadcast over the USB consists of a combination of packets. These packets are combined to define individual transactions that are performed as part of a larger transfer. Each transaction type is defined, along with the individual packets that comprise them.

Chapter 8: Interrupt, Bulk, and Isochronous transfers require that the successful delivery of data be verified by USB. CRC and other error checking is performed to verify data delivery and if errors occur retries of the failed transmission are performed. This chapter discusses the various sources of errors and the error detection mechanisms used by USB to identify them, and the error recovery that is performed to overcome them.

Chapter 9: USB devices support power conservation by entering a suspended state. This chapter discusses the ways that devices are placed into the suspended state under software control. It also discusses how software re-awakens devices, and how a device such as a modem can initiate a wakeup remotely.

Part III: High Speed Device Operation

Chapter 10: This chapter provides a brief introduction to high-speed device operation and set the stage for a detailed discussion of the high-speed environment.

Chapter 11: High-speed capable devices must also be able to communicate in the full-speed signaling environment. High-speed devices add many extensions to the full-speed environment to permit reliable signaling at a 480Mb/s rate. This chapter introduces the principles associated with USB high-speed signalling and the methods used to switch between full- and high-speed operation.

Chapter 12: This chapter introduces the changes brought about by high-speed transmission rates. The transfers defined in USB 1.0 have the same primary characteristics in the high-speed environment. However, packet sizes and differences in signaling change accounts for some change. Also, new features have been added to the high-speed environment such as high-bandwidth transfers and ping protocol. These and other changes are review in this chapter.

Chapter 13: Error detection and handling during high-speed transactions is very similar in concept to the low- and full-speed error detection methods. However, due to the faster clock rates several of the timing parameters must be changed to support error detection implementations such as timout values and babble detect.

Chapter 14: This chapter discusses the changes required for high-speed devices to use the full-speed suspend and resume protocol and signaling conventions.

Part IV: USB 2.0 Hub Operation with LS/FS/HS Devices

Chapter 15: This chapter introduces the primary characteristic of a high-speed hub. It must be able to operate when attached to both full-speed and high-speed ports, and must support all device speeds on its ports.

Chapter 16: This chapter discusses the 2.0 hubs behavior when it receives high-speed packets on its upstream and downstream ports. This chapter details the operation of the high-speed repeater and discusses the delays associated with forwarding high-speed packets across the hub.

Chapter 17: This chapter introduces the concept of split transactions that allow high-speed hubs to support low- and full-speed devices without sacrificing large amounts of bus time required to access the slower devices. The operation of the transaction translator is described, along with the various forms of split transaction and the specific sequences employed by each.

Part V: USB Configuration

Chapter 18: This chapter provides an overview of the configuration process. Each of the major steps involved in USB device enumeration are defined and discussed.

Chapter 19: This chapter discusses configuration of USB devices that are attached to any USB port. The process is virtually the same for devices of any speed. Device descriptors and other characteristics and features that relate to configuring the device are also detailed and discussed.

Chapter 20: Hub devices are configured like any other device attached to a USB port. Hub configuration differs in that it involves reporting whether or not other devices are attached to the downstream ports. This chapter review the hub configuration process with the focus on the issues related to extending the bus through the hub's downstream facing ports.

Chapter 21: This chapter introduces the concept of device classes and discusses their role within the USB. This chapter discusses the first five class types that were defined. These class are discussed to provide the reader with a sense of the information defined for each class and the USB mechanisms that they use. A detailed discussion of device classes requires in-depth knowledge in the associated field such as telephony and audio.

Part VI: USB Software

Chapter 22: Host software consists of three types of components: the USB Device Drivers, the USB Driver, and the Host Controller Driver. This chapter discusses the role of each of these layers and describes the requirements of their programming interface.

Who Should Read this Book

This book is intended for use by hardware and software design and support personnel. Those individuals working outside of the design field may also find the text useful.

Prerequisite Knowledge

The reader should be familiar with PC Architectures and legacy hardware and software issues. MindShare's ISA System Architecture book provides foundation material that describes the legacy issues.

Visit Our Web Page

Our web site contains a listing of all of our courses and books. In addition, it contains errata for a number of the books, a hot link to our publisher's web site, as well as course outlines.

www.mindshare.com

Our publisher's web page contains a listing or our currently-available books and includes pricing and ordering information. Their home page is accessible at:

www.aw.com/cseng


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Table of Contents

About This Book
The MindShare Architecture Series 1
Cautionary Note 2
Specifications This Book is Based On 3
Organization of This Book 3
Who Should Read this Book 7
Prerequisite Knowledge 7
Documentation Conventions 8
Identification of Bit Fields (logical groups of bits or signals) 9
Visit Our Web Page 9
We Want Your Feedback 9
Part 1 Overview of USB 2.0
Chapter 1 Design Goals of USB
Shortcomings of the Original PC I/O Paradigm 13
The USB Paradigm 18
How to Get the USB Specifications 24
Chapter 2 The Big Picture
Overview 25
USB 1.x Systems and Devices 28
2.0 Systems and Devices 37
The Players 44
USB Communications Model 54
Device Framework (how devices present themselves to software) 60
USB Peripheral Connection 66
Topology 67
Chapter 3 Cables and Connectors
The Connectors 69
Cables 71
Electrical and Mechanical Specifications 74
Chapter 4 USB Cable Power Distribution
USB Power 75
Hubs 76
Bus-Powered Hubs 80
Bus-Powered Devices 82
Self-Powered Hubs 86
Self-Powered Devices 89
Part 2 Low- & Full-Speed Device Operation
Chapter 5 LS/FS Signaling Environment
Overview 93
Detecting Device Attachment and Speed Detect 94
Bus Idle 102
Device RESET 103
Differential Signaling 104
NRZI Encoding 111
Bit Stuffing 112
Summary of USB Signaling States 113
Chapter 6 LS/FS Transfer Types & Scheduling
Overview 117
Client Initiates Transfer 118
Frame-Based Transfers 121
Transfer Types 122
Chapter 7 Packets & Transactions
Overview 141
Packets--The Basic Building Blocks of USB Transactions 143
Token Packets 147
Data Packets--DATA0 and Data1 152
Handshake Packets 153
Preamble Packet 154
Transactions 156
Chapter 8 Error Recovery
Overview 167
Packet Errors 168
Bus Time-Out 172
False EOPs 174
Data Toggle Errors 175
Special Case: Data Toggle During Control Transfer 188
Babbling Devices 189
Loss of Activity (LOA) 189
Babble/LOA Detection and Recovery 189
Isochronous Transfers (Delivery Not Guaranteed) 193
Interrupt Transfer Error Recovery 193
Bulk Transfer Error Recovery 193
Control Transfer Error Recovery 193
Chapter 9 USB Power Conservation
Power Conservation--Suspend 195
Global Suspend 197
Selective Suspend 201
Selective Suspend Followed by Global Suspend 206
Resume via Reset 206
Part 3 High Speed Device Operation
Chapter 10 Overview of HS Device Operation
Overview 213
New High-Speed Device Features 214
1.x USB Device Support 214
The 2.0 Host Controller 216
Chapter 11 The High-Speed Signaling Environment
Overview 217
Detecting High-Speed Device Attachment 219
High-Speed Differential Signaling 224
High-Speed Start of Packet & Synchronization Sequence 234
High-Speed End of Packet (EOP) 236
Detection of High-Speed Device Removal 236
High-Speed RESET and Suspend 239
Chapter 12 HS Transfers, Transactions, & Scheduling
Overview 242
High-Speed Transaction Scheduling 242
Periodic Transfers 244
Non-Periodic Transfers 254
Chapter 13 HS Error Detection and Handling
Overview 265
High-Speed Bus Time-out 266
False EOP 267
HS Babbling Device Detection 268
Chapter 14 HS Suspend and Resume
Overview 271
Entering Device Suspend 272
Device Resume 273
Part 4 USB 2.0 Hub Operation with LS/FS/HS Devices
Chapter 15 HS Hub Overview
Overview 277
USB 2.0 Hub Attached to High-Speed Port 278
USB 2.0 Hub Attached to Full-Speed Port 281
Chapter 16 2.0 Hubs During HS Transactions
Overview 283
High-Speed Hub Repeater 284
Chapter 17 2.0 Hubs During LS/FS Transactions
Overview 289
The Structure of Split Transactions 290
The Split Token Packet 296
The Transaction Translator 297
Split Transaction Scheduling 300
Periodic Split Transactions 310
Non Periodic Split Transactions 327
Part 5 USB Device Configuration
Chapter 18 Configuration Process
Overview 339
The Configuration Software Elements 341
Root Hub Configuration 343
Chapter 19 USB Device Configuration
Overview 347
Summary of Configuration Process 348
How Software Detects Device Attachment & Speed 348
Resetting the Port 352
Reading and Interpreting the USB Descriptors 353
Device States 371
Client Software Configuration 374
Chapter 20 Hub Configuration
Configuring the Hub 376
Reading the Hub's Descriptors 377
1.x Hub Descriptors 378
High-Speed Capable Hub Descriptors 391
Powering the Hub 397
Checking Hub Status 397
Summary of Hub Port States 399
Chapter 21 Device Classes
Overview 403
Device Classes 406
Audio Device Class 407
Communications Device Class 410
Display Device Class 412
Mass Storage Device Class 414
Part 6 USB Software Overview
Chapter 22 Overview of USB Host Software
USB Software 421
USB Driver (USBD) 426
Configuration Management 426
Data Transfer Management 429
Providing Client Services (The USB Driver Interface) 430
Appendix
Appendix A Standard Device Requests
Overview 435
Standard Device Requests 436
Set/Clear Feature 439
Set/Get Configuration 440
Set/Get Descriptor 440
Set/Get Interface 441
Get Status 442
Sync Frame 444
Device Tests 444
Appendix B Hub Requests
Overview 447
Hub Request Types 448
Hub Class Requests 450
Get/Set Descriptor Request 452
Get Hub Status Request 452
Set/Clear Hub Feature Request 455
Get Port Status Request 456
Set/Clear Port Feature 461
Port Test Modes 462
Get Bus State 463
Appendix C Universal Host Controller
Overview 465
Universal Host Controller Transaction Scheduling 465
Transfer Descriptors 468
Queue Heads 473
UHC Control Registers 474
Appendix D Open Host Controller
Overview 477
Open Host Controller Transfer Scheduling 477
Endpoint Descriptors 483
The Open Host Controller Registers 492
Index 495
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Preface

PREFACE:

The MindShare Architecture Series

The MindShare Architecture book series includes: ISA System Architecture, EISA System Architecture, 80486 System Architecture, PCI System Architecture, Pentium System Architecture, PCMCIA System Architecture, PowerPC System Architecture, Plug-and-Play System Architecture, CardBus System Architecture, Protected Mode Software Architecture, Pentium Pro and Pentium II System Architecture, USB System Architecture, FireWire System Architecture, PCI-X System Architecture, and AGP System Architecture. The book series is published by Addison-Wesley.

Rather than duplicating common information in each book, the series uses the building-block approach. ISA System Architecture is the core book upon which the others build. Table 1 on page 1 illustrates the relationship of the books to each other.

Cautionary Note

The reader should keep in mind that MindShare's book series often deals with rapidly-evolving technologies. This being the case, it should be recognized that the book is a "snapshot" of the state of the targeted technology at the time that the book was completed. We attempt to update each book on a timely basis to reflect changes in the targeted technology, but, due to various factors (waiting for the next version of the spec to be "frozen," the time necessary to make the changes, and the time to produce the books and get them out to the distribution channels), there will always be a delay.

Specifications This Book is Based On

This book is based on the Universal Serial Bus 2.0 specification.

Organization of This Book

The book is divided into sixpartsand contains the chapters listed below:

Part I: Overview of USB 2.0

Chapter 1: This chapter provides an overview of the primary concepts of USB transfers and describes the interaction between USB system software, system hardware, and USB devices for USB 1.x systems and USB 2.0 system. The USB communications process is described, including the concept of the device framework. Each hardware and software element in a USB system is introduced and its primary functions are described.

Chapter 2: This chapter provides an overview of the primary concepts of USB transfers and describes the interaction between USB system software, system hardware, and USB devices for USB 1.x systems and USB 2.0 system. The USB communications process is described, including the concept of the device framework. Each hardware and software element in a USB system is introduced and its primary functions are described.

Chapter 3: USB defines a single connector type for attaching all USB peripherals to the host system. This chapter introduces the physical aspects of USB connectors and cables.

Chapter 4: This chapter discusses USB power distribution, along with issues related to bus powered devices and the operation of self-powered devices. The chapter also discusses the role of host software in detecting and reporting power related problems.

Part II: The USB Solution

Chapter 5: USB employs NRZI encoding and differential signaling to transfer information across USB cables. This chapter discusses the low- and full-speed signaling environment, including the differential signaling and NRZI encoding techniques used by the USB. The signaling environment must also support a wide range of other signal-related functions such as: detecting device attachment and removal, suspending and resuming operation, resetting a device, and others all of which are discussed in this chapter.

Chapter 6: USB supports four transfer types: interrupt, bulk, isochronous, and control. These transfer types and the process used to initiate and perform them are described in this chapter.

Chapter 7: Every transfer broadcast over the USB consists of a combination of packets. These packets are combined to define individual transactions that are performed as part of a larger transfer. Each transaction type is defined, along with the individual packets that comprise them.

Chapter 8: Interrupt, Bulk, and Isochronous transfers require that the successful delivery of data be verified by USB. CRC and other error checking is performed to verify data delivery and if errors occur retries of the failed transmission are performed. This chapter discusses the various sources of errors and the error detection mechanisms used by USB to identify them, and the error recovery that is performed to overcome them.

Chapter 9: USB devices support power conservation by entering a suspended state. This chapter discusses the ways that devices are placed into the suspended state under software control. It also discusses how software re-awakens devices, and how a device such as a modem can initiate a wakeup remotely.

Part III: High Speed Device Operation

Chapter 10: This chapter provides a brief introduction to high-speed device operation and set the stage for a detailed discussion of the high-speed environment.

Chapter 11: High-speed capable devices must also be able to communicate in the full-speed signaling environment. High-speed devices add many extensions to the full-speed environment to permit reliable signaling at a 480Mb/s rate. This chapter introduces the principles associated with USB high-speed signalling and the methods used to switch between full- and high-speed operation.

Chapter 12: This chapter introduces the changes brought about by high-speed transmission rates. The transfers defined in USB 1.0 have the same primary characteristics in the high-speed environment. However, packet sizes and differences in signaling change accounts for some change. Also, new features have been added to the high-speed environment such as high-bandwidth transfers and ping protocol. These and other changes are review in this chapter.

Chapter 13: Error detection and handling during high-speed transactions is very similar in concept to the low- and full-speed error detection methods. However, due to the faster clock rates several of the timing parameters must be changed to support error detection implementations such as timout values and babble detect.

Chapter 14: This chapter discusses the changes required for high-speed devices to use the full-speed suspend and resume protocol and signaling conventions.

Part IV: USB 2.0 Hub Operation with LS/FS/HS Devices

Chapter 15: This chapter introduces the primary characteristic of a high-speed hub. It must be able to operate when attached to both full-speed and high-speed ports, and must support all device speeds on its ports.

Chapter 16: This chapter discusses the 2.0 hubs behavior when it receives high-speed packets on its upstream and downstream ports. This chapter details the operation of the high-speed repeater and discusses the delays associated with forwarding high-speed packets across the hub.

Chapter 17: This chapter introduces the concept of split transactions that allow high-speed hubs to support low- and full-speed devices without sacrificing large amounts of bus time required to access the slower devices. The operation of the transaction translator is described, along with the various forms of split transaction and the specific sequences employed by each.

Part V: USB Configuration

Chapter 18: This chapter provides an overview of the configuration process. Each of the major steps involved in USB device enumeration are defined and discussed.

Chapter 19: This chapter discusses configuration of USB devices that are attached to any USB port. The process is virtually the same for devices of any speed. Device descriptors and other characteristics and features that relate to configuring the device are also detailed and discussed.

Chapter 20: Hub devices are configured like any other device attached to a USB port. Hub configuration differs in that it involves reporting whether or not other devices are attached to the downstream ports. This chapter review the hub configuration process with the focus on the issues related to extending the bus through the hub's downstream facing ports.

Chapter 21: This chapter introduces the concept of device classes and discusses their role within the USB. This chapter discusses the first five class types that were defined. These class are discussed to provide the reader with a sense of the information defined for each class and the USB mechanisms that they use. A detailed discussion of device classes requires in-depth knowledge in the associated field such as telephony and audio.

Part VI: USB Software

Chapter 22: Host software consists of three types of components: the USB Device Drivers, the USB Driver, and the Host Controller Driver. This chapter discusses the role of each of these layers and describes the requirements of their programming interface.

Who Should Read this Book

This book is intended for use by hardware and software design and support personnel. Those individuals working outside of the design field may also find the text useful.

Prerequisite Knowledge

The reader should be familiar with PC Architectures and legacy hardware and software issues. MindShare's ISA System Architecture book provides foundation material that describes the legacy issues.

Visit Our Web Page

Our web site contains a listing of all of our courses and books. In addition, it contains errata for a number of the books, a hot link to our publisher's web site, as well as course outlines.

www.mindshare.com

Our publisher's web page contains a listing or our currently-available books and includes pricing and ordering information. Their home page is accessible at:

www.aw.com/cseng


Read More Show Less

Introduction

The MindShare Architecture Series

The MindShare Architecture book series includes: ISA System Architecture, EISA System Architecture, 80486 System Architecture, PCI System Architecture, Pentium System Architecture, PCMCIA System Architecture, PowerPC System Architecture, Plug-and-Play System Architecture, CardBus System Architecture, Protected Mode Software Architecture, Pentium Pro and Pentium II System Architecture, USB System Architecture, FireWire System Architecture, PCI-X System Architecture, and AGP System Architecture. The book series is published by Addison-Wesley.

Rather than duplicating common information in each book, the series uses the building-block approach. ISA System Architecture is the core book upon which the others build. Table 1 on page 1 illustrates the relationship of the books to each other.

Cautionary Note

The reader should keep in mind that MindShare's book series often deals with rapidly-evolving technologies. This being the case, it should be recognized that the book is a "snapshot" of the state of the targeted technology at the time that the book was completed. We attempt to update each book on a timely basis to reflect changes in the targeted technology, but, due to various factors (waiting for the next version of the spec to be "frozen," the time necessary to make the changes, and the time to produce the books and get them out to the distribution channels), there will always be a delay.

Specifications This Book is Based On

This book is based on the Universal Serial Bus 2.0 specification.

Organization of This Book

The book is divided into six parts andcontains the chapters listed below:

Part I: Overview of USB 2.0

Chapter 1: This chapter provides an overview of the primary concepts of USB transfers and describes the interaction between USB system software, system hardware, and USB devices for USB 1.x systems and USB 2.0 system. The USB communications process is described, including the concept of the device framework. Each hardware and software element in a USB system is introduced and its primary functions are described.

Chapter 2: This chapter provides an overview of the primary concepts of USB transfers and describes the interaction between USB system software, system hardware, and USB devices for USB 1.x systems and USB 2.0 system. The USB communications process is described, including the concept of the device framework. Each hardware and software element in a USB system is introduced and its primary functions are described.

Chapter 3: USB defines a single connector type for attaching all USB peripherals to the host system. This chapter introduces the physical aspects of USB connectors and cables.

Chapter 4: This chapter discusses USB power distribution, along with issues related to bus powered devices and the operation of self-powered devices. The chapter also discusses the role of host software in detecting and reporting power related problems.

Part II: The USB Solution

Chapter 5: USB employs NRZI encoding and differential signaling to transfer information across USB cables. This chapter discusses the low- and full-speed signaling environment, including the differential signaling and NRZI encoding techniques used by the USB. The signaling environment must also support a wide range of other signal-related functions such as: detecting device attachment and removal, suspending and resuming operation, resetting a device, and others all of which are discussed in this chapter.

Chapter 6: USB supports four transfer types: interrupt, bulk, isochronous, and control. These transfer types and the process used to initiate and perform them are described in this chapter.

Chapter 7: Every transfer broadcast over the USB consists of a combination of packets. These packets are combined to define individual transactions that are performed as part of a larger transfer. Each transaction type is defined, along with the individual packets that comprise them.

Chapter 8: Interrupt, Bulk, and Isochronous transfers require that the successful delivery of data be verified by USB. CRC and other error checking is performed to verify data delivery and if errors occur retries of the failed transmission are performed. This chapter discusses the various sources of errors and the error detection mechanisms used by USB to identify them, and the error recovery that is performed to overcome them.

Chapter 9: USB devices support power conservation by entering a suspended state. This chapter discusses the ways that devices are placed into the suspended state under software control. It also discusses how software re-awakens devices, and how a device such as a modem can initiate a wakeup remotely.

Part III: High Speed Device Operation

Chapter 10: This chapter provides a brief introduction to high-speed device operation and set the stage for a detailed discussion of the high-speed environment.

Chapter 11: High-speed capable devices must also be able to communicate in the full-speed signaling environment. High-speed devices add many extensions to the full-speed environment to permit reliable signaling at a 480Mb/s rate. This chapter introduces the principles associated with USB high-speed signalling and the methods used to switch between full- and high-speed operation.

Chapter 12: This chapter introduces the changes brought about by high-speed transmission rates. The transfers defined in USB 1.0 have the same primary characteristics in the high-speed environment. However, packet sizes and differences in signaling change accounts for some change. Also, new features have been added to the high-speed environment such as high-bandwidth transfers and ping protocol. These and other changes are review in this chapter.

Chapter 13: Error detection and handling during high-speed transactions is very similar in concept to the low- and full-speed error detection methods. However, due to the faster clock rates several of the timing parameters must be changed to support error detection implementations such as timout values and babble detect.

Chapter 14: This chapter discusses the changes required for high-speed devices to use the full-speed suspend and resume protocol and signaling conventions.

Part IV: USB 2.0 Hub Operation with LS/FS/HS Devices

Chapter 15: This chapter introduces the primary characteristic of a high-speed hub. It must be able to operate when attached to both full-speed and high-speed ports, and must support all device speeds on its ports.

Chapter 16: This chapter discusses the 2.0 hubs behavior when it receives high-speed packets on its upstream and downstream ports. This chapter details the operation of the high-speed repeater and discusses the delays associated with forwarding high-speed packets across the hub.

Chapter 17: This chapter introduces the concept of split transactions that allow high-speed hubs to support low- and full-speed devices without sacrificing large amounts of bus time required to access the slower devices. The operation of the transaction translator is described, along with the various forms of split transaction and the specific sequences employed by each.

Part V: USB Configuration

Chapter 18: This chapter provides an overview of the configuration process. Each of the major steps involved in USB device enumeration are defined and discussed.

Chapter 19: This chapter discusses configuration of USB devices that are attached to any USB port. The process is virtually the same for devices of any speed. Device descriptors and other characteristics and features that relate to configuring the device are also detailed and discussed.

Chapter 20: Hub devices are configured like any other device attached to a USB port. Hub configuration differs in that it involves reporting whether or not other devices are attached to the downstream ports. This chapter review the hub configuration process with the focus on the issues related to extending the bus through the hub's downstream facing ports.

Chapter 21: This chapter introduces the concept of device classes and discusses their role within the USB. This chapter discusses the first five class types that were defined. These class are discussed to provide the reader with a sense of the information defined for each class and the USB mechanisms that they use. A detailed discussion of device classes requires in-depth knowledge in the associated field such as telephony and audio.

Part VI: USB Software

Chapter 22: Host software consists of three types of components: the USB Device Drivers, the USB Driver, and the Host Controller Driver. This chapter discusses the role of each of these layers and describes the requirements of their programming interface.

Who Should Read this Book

This book is intended for use by hardware and software design and support personnel. Those individuals working outside of the design field may also find the text useful.

Prerequisite Knowledge

The reader should be familiar with PC Architectures and legacy hardware and software issues. MindShare's ISA System Architecture book provides foundation material that describes the legacy issues.

Visit Our Web Page

Our web site contains a listing of all of our courses and books. In addition, it contains errata for a number of the books, a hot link to our publisher's web site, as well as course outlines.

Read More Show Less

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Our reader reviews allow you to share your comments on titles you liked, or didn't, with others. By submitting an online review, you are representing to Barnes & Noble.com that all information contained in your review is original and accurate in all respects, and that the submission of such content by you and the posting of such content by Barnes & Noble.com does not and will not violate the rights of any third party. Please follow the rules below to help ensure that your review can be posted.

Reviews by Our Customers Under the Age of 13

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