UNIX Systems for Modern Architectures: Symmetric Multiprocessing and Caching for Kernel Programmers / Edition 1

UNIX Systems for Modern Architectures: Symmetric Multiprocessing and Caching for Kernel Programmers / Edition 1

by Curt Schimmel
     
 

ISBN-10: 0201633388

ISBN-13: 9780201633382

Pub. Date: 07/28/1994

Publisher: Addison-Wesley

This book represents a significant new milestone in UNIX kernel internals books. Symmetric multiprocessing and cache memory systems are important cost-effective technologies for improving performance in today's state-of-the-art systems.

Written for the UNIX kernel developer, this book provides a complete yet comprehensible explanation of the operation of caches

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Overview

This book represents a significant new milestone in UNIX kernel internals books. Symmetric multiprocessing and cache memory systems are important cost-effective technologies for improving performance in today's state-of-the-art systems.

Written for the UNIX kernel developer, this book provides a complete yet comprehensible explanation of the operation of caches and symmetric multiprocessors, how they work together, and the issues operating systems must address in order to run on the machines that incorporate them.

After a review of UNIX kernel internals, Curt Schimmel launches into a detailed description of cache memory systems, including several kinds of virtual and physical caches, as well as a chapter on efficient cache management. For each type of cache, the book covers the impact on the software and the operating system changes necessary for these systems. The next section details the operation of the tightly-coupled, shared memory, symmetric multiprocessor. It examines the problems these multiprocessors present to the operating system, such as race conditions, deadlocks, and the ordering of memory operations, and looks at how the UNIX kernel can be adapted to run on such systems. Finally, the book looks at the interaction between cache memory systems and multiprocessors and the new problems that this interaction presents to the kernel. Techniques for solving these problems are then explained.

Numerous examples representing CISC and RISC processors, such as the Intel 80486 and Pentium, the Motorola 68040 and 88000, as well as theMIPS and SPARC processors, illustrate the concepts presented. To reinforce the concepts, each chapter contains a set of exercises with answers to selected exercises included in the back.

"This book UNIX Systems for Modern Architectures for the systems programmer covers almost everything you wanted to know about caches, multiprocessor systems, and cached multiprocessor systems, especially as related to UNIX."-Unix Review

0201633388B04062001

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Product Details

ISBN-13:
9780201633382
Publisher:
Addison-Wesley
Publication date:
07/28/1994
Series:
Addison-Wesley Professional Computing Series
Edition description:
New Edition
Pages:
432
Product dimensions:
7.10(w) x 9.00(h) x 1.10(d)

Table of Contents

Preface.

Notational Conventions.

Introduction.

1. Review of UNIX Kernel Internals.

Introduction.

Processes, Programs, and Threads.

The Process Address Space.

Context Switch.

Memory and Process Management System Calls.

Summary.

Exercises.

Further Reading.

I. CACHE MEMORY SYSTEMS. @CHAPTER 2. Introduction to Cache Memory Systems.

Memory Hierarchies.

Cache Fundamentals.

Direct Mapped Caches.

Two-Way Set Associative Caches.

n-Way Set Associative Caches.

Fully Associative Caches.

Summary of n-Way Set Associative Caches.

Cache Flushing.

Uncached Operation.

Separate Instruction and Data Caches.

Cache Performance.

How Cache Architectures Differ.

Exercises.

Further Reading.

3. Virtual Caches.

Virtual Cache Operation.

Problems with Virtual Caches.

Managing a Virtual Cache.

Summary.

Exercises.

Further Reading.

4. Virtual Caches with Keys.

The Operation of a Virtual Cache with Keys.

Managing a Virtual Cache with Keys.

Virtual Cache Usage in MMUs.

Summary.

Exercises.

Further Reading.

5. Virtual Caches with Physical Address Tags.

The Organization of a Virtual Cache with Physical Tags.

Managing a Virtual Cache with Physical Tags.

Summary.

Exercises.

Further Reading.

6. Physical Caches.

The Organization of a Physical Cache.

Managing a Physical Cache.

Multilevel Caches.

Primary Virtual Cache with Secondary Physical Cache.

Summary.

Exercises.

Further Reading.

7. Efficient Cache Management Techniques.

Introduction.

Address Space Layout.

Cache Size Bounded Flushing—Delayed Cache Invalidations.

Cache-Aligning Data Structures.

Summary.

Exercises.

Further Reading.

II. MULTIPROCESSOR SYSTEMS.

8. Introduction to Multiprocessor Systems.

Introduction.

The Tightly Coupled, Shared Memory, Symmetric.

Multiprocessor.

The MP Memory Model.

Mutual Exclusion.

Review of Mutual Exclusion on Uniprocessor.

UNIX Systems.

Problems Using UP Mutual Exclusion Policies on MPs.

Summary.

Exercises.

Further Reading.

9. Master-Slave Kernels.

Introduction.

Spin Locks.

Deadlocks.

Master-Slave Kernel Implementation.

Performance Considerations.

Summary.

Exercises.

Further Reading.

10. Spin-Locked Kernels.

Introduction.

Giant Locking.

Multithreading Cases Requiring No Locks.

Coarse-Grained Locking.

Fine-Grained Locking.

Effects of Sleep and Wakeup on Multiprocessors.

Summary.

Exercises.

Further Reading.

11. Semaphored Kernels.

Introduction.

Deadlocks.

Implementing Semaphores.

Coarse-Grained Semaphore Implementations.

Multithreading with Semaphores.

Performance Considerations.

Summary.

Exercises.

Further Reading.

12. Other MP Primitives.

Introduction.

Monitor.

Eventcounts and Sequencers.

The MP Primitives of SVR4.2 MP.

Comparison of MP Synchronization Primitives.

Summary.

Exercises.

Further Reading.

13. Other Memory Models.

Introduction.

Dekker's Algorithm.

Other Memory Models.

Total Store Ordering.

Partial Store Ordering.

The Store Buffer as Part of the Memory Hierarchy.

Summary.

Exercises.

Further Reading.

III. MULTIPROCESSOR SYSTEMS WITH CACHES.

14. Introduction to MP Cache Consistency.

Introduction.

The Cache Consistency Problem.

Software Cache Consistency.

Summary.

Exercise.

Further Reading.

15. Hardware Cache Consistency.

Introduction.

Write-Invalidate Protocols.

Write-Update Protocols.

Consistency of Read-Modify-Write Operations.

Hardware Consistency for Multilevel Caches.

Other Main Memory Architectures.

Effects on the Software.

Hardware Consistency for Nonsequential Memory Models.

Performance Considerations for Software.

Summary.

Exercises.

Further Reading.

Appendix A: Architecture Summary.

Appendix B: Answers to Selected Exercises.

Index. 0201633388T04062001

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