Variation-Aware Analog Structural Synthesis: A Computational Intelligence Approach / Edition 1

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Overview

Variation-Aware Analog Structural Synthesis describes computational intelligence-based tools for robust design of analog circuits. It starts with global variation-aware sizing and knowledge extraction, and progressively extends to variation-aware topology design. The computational intelligence techniques developed in this book generalize beyond analog CAD, to domains such as robotics, financial engineering, automotive design, and more.

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Editorial Reviews

From the Publisher
From the reviews:

“This book is squarely aimed at analog circuit designers who are searching for new approaches to analog structural design and optimization. … Those most likely to benefit from this book … are experts in the field of industrial circuit design seeking insight into new design tools. … for the non-expert, with only a cursory understanding of the background material, the processes and results described in this book are an inspiring example of real-world applications of evolutionary design.” (John Rieffel, Genetic Programming and Evolvable Machines, Vol. 12, 2011)

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Product Details

  • ISBN-13: 9789048129058
  • Publisher: Springer Netherlands
  • Publication date: 7/21/2009
  • Series: Analog Circuits and Signal Processing Series
  • Edition description: 2009
  • Edition number: 1
  • Pages: 306
  • Product dimensions: 9.21 (w) x 6.14 (h) x 0.75 (d)

Meet the Author

Trent McConaghy is co-founder and Chief Scientific Officer of Solido Design Automation Inc. He was a co-founder and Chief Scientist of Analog Design Automation Inc., which was acquired by Synopsys Inc. in 2004. Prior to that, he did research for the Canadian Department of National Defense. He received his PhD degree in Electrical Engineering from the Katholieke Universiteit Leuven, Belgium, in 2008. He received a Bachelor’s in Engineering (with great distinction), and a Bachelor’s in Computer Science (with great distinction), both from the University of Saskatchewan, Canada, in 1999. He has about 40 peer-reviewed technical papers and patents granted / pending. He has given invited talks / tutorials at many labs, universities, and conferences such as JPL, MIT, ICCAD, and DAC. He is regularly a technical program committee member and reviewer in both the CAD and intelligent systems fields, such as IEEE Trans CAD, ACM TODAES, Electronics Letters, to IEEE Trans Evolutionary Computation, the Journal of Genetic Programming and Evolvable Machines, GPTP, GECCO, ICES, etc. His research interest is in statistical machine learning and intelligent systems, with transistor-level CAD applications such as variation-aware design, analog topology design, automated sizing, knowledge extraction, and symbolic modeling.

Michiel Steyaert was born in Aalst, Belgium, in 1959. He received the masters degree in electrical-mechanical engineering and the Ph.D. degree in electronics from the Katholieke Universiteit Leuven (K.U.Leuven), Heverlee, Belgium in 1983 and 1987, respectively. From 1983 to 1986 he obtained an IWNOL fellowship (Belgian National Fundation for Industrial Research) which allowed him to work as a Research Assistant at the Laboratory ESAT at K.U.Leuven. In 1987 he was responsible for several industrial projects in the field of analog micropower circuits at the Laboratory ESAT as an IWONL Project Researcher. In 1988 he was a Visiting Assistant Professor at the University of California, Los Angeles. In 1989 he was appointed by the National Fund of Scientific Research (Belgium) as Research Associate, in 1992 as a Senior Research Associate and in 1996 as a Research Director at the Laboratory ESAT, K.U.Leuven. Between 1989 and 1996 he was also a part-time Associate Professor. He is now a Full Professor at the K.U.Leuven. His current research interests are in high-performance and high-frequency analog integrated circuits for telecommunication systems and analog signal processing. Prof.Steyaert received the 1990 and 2001 European Solid-State Circuits Conference Best Paper Award. He received the 1991 and the 2000 NFWO Alcatel-Bell-Telephone award for innovative work in integrated circuits for telecommunications. Prof.Steyaert received the 1995 and 1997 IEEE-ISSCC Evening Session Award, the 1999 IEEE Circuit and Systems Society Guillemin-Cauer Award and is currently an IEEE-Fellow.

Georges Gielen received the MSc and PhD degrees in Electrical Engineering from the Katholieke Universiteit Leuven, Belgium, in 1986 and 1990, respectively. He currently is a Full Professor at the Katholieke Universiteit Leuven. His research interests are in the design of analog and mixed-signal integrated circuits, and especially in analog and mixed-signal CAD tools and design automation (modeling, simulation and symbolic analysis, analog synthesis, analog layout generation, analog and mixed-signal testing). He is coordinator or partner of several (industrial) research projects in this area, including several European projects (EU, MEDEA, ESA). He has authored or coauthored five books and more than 300 papers in edited books, international journals and conference proceedings. He regularly is a member of the Program Committees of international conferences (DAC, ICCAD, ISCAS, DATE, CICC...), and served as General Chair of the DATE conference in 2006 and of the International Conference on Computer-Aided Design in 2007. He serves regularly as member of editorial boards of international journals (IEEE Transactions on Circuits and Systems, Springer international journal on Analog Integrated Circuits and Signal Processing, Elsevier Integration). He received the 1995 Best Paper Award in the John Wiley international journal on Circuit Theory and Applications, and was the 1997 Laureate of the Belgian Royal Academy on Sciences, Literature and Arts in the discipline of Engineering. He received the 2000 Alcatel Award from the Belgian National Fund of Scientific Research for his innovative research in telecommunications, and won the DATE 2004 Best Paper Award. He is a Fellow of the IEEE, served as elected member of the Board of Governors of the IEEE Circuits And Systems (CAS) society and as chairman of the IEEE Benelux CAS chapter. He served as the President of the IEEE Circuits And Systems (CAS) Society in 2005. He was elected DATE Fellow in 2007, and received the IEEE Computer Society Outstanding Contribution Award and the IEEE Circuits and Systems Society Meritorious Service Award in 2007.

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Table of Contents

Preface. Acronyms and Notation.
1. INTRODUCTION. 1.1 Motivation. 1.2 Background and Contributions to Analog CAD. 1.3 Background and Contributions to AI. 1.4 Analog CAD Is a Fruitfly for AI. 1.5 Conclusion.
2. VARIATION-AWARE SIZING: BACKGROUND. 2.1 Introduction and Problem Formulation. 2.2 Review of Yield Optimization Approaches. 2.3 Conclusion.
3. GLOBALLY RELIABLE, VARIATION-AWARE SIZING: SANGRIA. 3.1 Introduction. 3.2 Foundations: Model-Building Optimization (MBO). 3.3 Foundations: Shastic Gradient Boosting. 3.4 Foundations: Homotopy. 3.5 SANGRIA Algorithm. 3.6 SANGRIA Experimental Results. 3.7 On Scaling to Larger Circuits. 3.8 Conclusion.
4. KNOWLEDGE EXTRACTION IN SIZING: CAFFEINE. 4.1 Introduction and Problem Formulation. 4.2 Background: GP and Symbolic Regression. 4.3 CAFFEINE Canonical Form Functions. 4.4 CAFFEINE Search Algorithm. 4.5 CAFFEINE Results. 4.6 Scaling Up CAFFEINE: Algorithm. 4.7 Scaling Up CAFFEINE: Results. 4.8 Application: Behaviorial Modeling. 4.9 Application: Process-Variable Robustness Modeling. 4.10 Application: Design-Variable Robustness Modeling. 4.11 Application: Automated Sizing. 4.12 Application: Analytical Performance Tradeoffs. 4.13 Sensitivity To Search Algorithm. 4.14 Conclusion.
5. CIRCUIT TOPOLOGY SYNTHESIS: BACKGROUND. 5.1 Introduction. 5.2 Topology-Centric Flows. 5.3 Reconciling System-Level Design. 5.4 Requirements for a Topology Selection / Design Tool. 5.5 Open-Ended Synthesis and the Analog Problem Domain. 5.6 Conclusion.
6. TRUSTWORTHY TOPOLOGY SYNTHESIS: MOJITO SEARCH SPACE. 6.1 Introduction. 6.2 Search Space Framework. 6.3 A Highly Searchable Op Amp Library. 6.4 Operating-Point Driven Formulation. 6.5 Worked Example. 6.6 Size of Search Space. 6.7 Conclusion.
7. TRUSTWORTHY TOPOLOGY SYNTHESIS: MOJITO ALGORITHM. 7.1 Introduction. 7.2 High-Level Algorithm. 7.3 Search Operators. 7.4 Handling Multiple Objectives. 7.5 Generation of Initial Individuals. 7.6 Experimental Setup. 7.7 Experiment: Hit Target Topologies? 7.8 Experiment: Diversity? 7.9 Experiment: Human-Competitive Results? 7.10 Discussion: Comparison to Open-Ended Structural Synthesis. 7.11 Conclusion.
8. KNOWLEDGE EXTRACTION IN TOPOLOGY SYNTHESIS. 8.1 Introduction. 8.2 Generation of Database. 8.3 Extraction of Specs-To-Topology Decision Tree. 8.4 Global Nonlinear Sensitivity Analysis. 8.5 Extraction of Analytical Performance Tradeoffs. 8.6 Conclusion.
9. VARIATION-AWARE TOPOLOGY SYNTHESIS & KNOWLEDGE EXTRACTION. 9.1 Introduction. 9.2 Problem Specification. 9.3 Background. 9.4 Towards a Solution. 9.5 Proposed Approach: MOJITO-R. 9.6 MOJITO-R Experimental Validation. 9.7 Conclusion.
10. NOVEL VARIATION-AWARE TOPOLOGY SYNTHESIS. 10.1 Introduction. 10.2 Background. 10.3 MOJITO-N Algorithm and Results. 10.4 ISCLEs Algorithm And Results. 10.5 Conclusion.
11. CONCLUSION. 11.1 General Contributions. 11.2 Specific Contributions. 11.3 Future Work. 11.4 Final Remarks.

References. Index.

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