VERILOG-2001: A Guide to the New Features of the VERILOG Hardware Description Language

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Overview

The IEEE 1364-2001 standard, nicknamed 'Verilog-2001', is the first major update to the Verilog language since its inception in 1984. This book presents 45 significant enhancements contained in Verilog-2001 standard. A few of the new features described in this book are:

  • ANSI C style port declarations for modules, primitives, tasks and functions;
  • Automatic tasks and functions (re-entrant tasks and recursive functions);
  • Multidimensional arrays of ...
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Overview

The IEEE 1364-2001 standard, nicknamed 'Verilog-2001', is the first major update to the Verilog language since its inception in 1984. This book presents 45 significant enhancements contained in Verilog-2001 standard. A few of the new features described in this book are:

  • ANSI C style port declarations for modules, primitives, tasks and functions;
  • Automatic tasks and functions (re-entrant tasks and recursive functions);
  • Multidimensional arrays of any data type, plus array bit and part selects;
  • Signed arithmetic extensions, including signed data types and sign casting;
  • Enhanced file I/O capabilities, such as $fscanf, $fread and much more;
  • Enhanced deep submicron timing accuracy and glitch detection;
  • Generate blocks for creating multiple instances of modules and procedures;
  • Configurations for true source file management within the Verilog language.
This book assumes that the reader is already familiar with using Verilog. It supplements other excellent books on how to use the Verilog language, such as The Verilog Hardware Description Language, by Donald Thomas and Philip Moorby (Kluwer Academic Publishers, ISBN: 0-7923-8166-1) and Verilog Quickstart: A Practical Guide to Simulation and Synthesis, by James Lee (Kluwer Academic Publishers, ISBN: 0-7923-8515-2).

Editorial Reviews

The IEEE 1364-2001 standard, Verilog 2001, is the first major update to the Verilog language since its inception in 1984. This book presents 45 significant enhancements contained in the Verilog 2001 standard. Descriptions of new features are presented, along with ideas of how they can be useful in modeling and verifying designs. The description of each enhancement includes a note on whether the enhancement should be supported by synthesis tools. The reader is assumed to be familiar with Verilog. Sutherland is a member of the IEEE Verilog Standards Committee. Annotation c. Book News, Inc., Portland, OR (booknews.com)

Product Details

Table of Contents

Foreword; P. Moorby. Introduction. What's new in Verilog-2001. 1. Combined port and data type declarations. 2. ANSI C style module declarations. 3. Module port parameter lists. 4. ANSI C style UDP declarations. 5. Variable initial value at declaration. 6. ANSI C style task/function declarations. 7. Automatic (re-entrant) tasks. 8. Automatic (recursive) functions. 9. Constant functions. 10. Comma separated sensitivity lists. 11. Combinational logic sensitivity lists. 11. Combinational logic sensitivity lists. 12. Implicit nets for continuous assignments. 13. Disabling implicit net declarations. 14. Variable vector part selects. 15. Multidimensional arrays. 16. Arrays of net and real data types. 17. Array bit and part selects. 18. Signed reg, net and port declarations. 19. Signed based integer numbers. 20. Signed functions. 21. Sign conversion system functions. 22. Arithmetic shift operators. 23. Assignment width extension past 32 bits. 24. Power operator. 25. Attributes. 26. Sized and typed parameter constants. 27. Explicit in-line parameter redefinition. 28. Fixed local parameters. 29. Standard random number generator. 30. Extended number of open files. 31. Enhanced file I/O. 32. String read and write system tasks. 33. Enhanced invocation option testing. 34. Enhanced conditional compilation. 35. Source file and line compiler directive. 36. Generate blocks. 37. Configurations. 38. On-detect pulse error propagation. 39. Negative pulse detection. 40. Enhanced input timing checks. 41. Negative input timing constraints. 42. Enhanced SDF file support. 43. Extended VCD files. 44. Enhanced PLA system tasks. 45. Enhanced Verilog PLI support. Appendices. Index.

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