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This classic Verilog (IEEE Std 1364-1995) hardware description reference text has been updated and expanded once again to meet the requirements of university courses. The authors have taken an example-oriented approach to introduce Verilog. They concentrate on design specification and avoid specific detail on simulator and synthesis. Thus, students should be able to write working executable models after studying this text, regardless of the simulator or synthesis tools they use.
6.1 Overview of Synthesis
The predominate synthesis technology in use today is logic synthesis. A system is specified at the register-transfer level of design, and, by using logic synthesis tools, a gate level implementation of the system can be obtained. The synthesis tools are capable of optimizing a design with respect to various constraints, including timing and/or area. They use a technology library file to specify the components to be used in the design. Writing Verilog specifications for logic synthesis tools will be discussed in this chapter.
6.1.1 Register-Transfer Level Systems
A register- transfer level description may contain different features; parts of the description may be purely combinational while others may specify sequential elements such as latches and flip flops. There may also be a finite state machine description, specifying a state transition graph.
A logic synthesis tool compiles a register-transfer level design using two main phases. The first is a technology independent phase where the design is read in and manipulated without regard to the final implementation technology. In this phase, major simplifications in the combinational logic may be made. The second phase is technology mapping where the design is transformed to match the components in a component library. If there are only two-input gates in the library, the design is transformed so that each logic function is implementable by a component in the library. Indeed, synthesis tools can transform one gate level description into another, providing the capability of redesigning a circuit when a new technology library is used.
The attraction of a logic synthesis CAD tool is that it aids in a fairly complex design process. (After all, did your logic design professor ever tell you what to do when the Karnaugh map had more than five or six variables!) These tools target large combinational design and different technology libraries, providing implementation trade-offs in time and area. Further, they promise functional equivalence of the initial specification and its resulting implementation. Given the complexity of this level of design, these tools improve the productivity of designers in many common design situations.
To obtain this increased productivity, we must specify our design in a way that it can be simulated for functional correctness and then synthesized. Whereas the earlier parts of this book focussed on the semantics of the full language and how it can be used to model intricate timing and behavior, this chapter discusses methods of describing register-transfer level systems for input to logic synthesis tools.
The first part of this chapter defines what a synthesizable description for logic synthesis is. There are behaviors that we can describe but that common logic synthesis tools will not be able to design. (Or they may design something you'd want your competitor to implement!) Since synthesis technology is still young, and the task of mapping an arbitrary behavior on to a set of library components is complex, arbitrary behavior specifications are not allowed as inputs to logic synthesis tools. Thus, only a subset of the language may be used for logic synthesis, and the style of writing a description using that subset is restricted. The first part of this chapter describes the subset and restrictions commonly found in logic synthesis specification today. As logic synthesis technology matures, the set of allowable constructs will probably expand and the style restrictions will probably lessen; -hey both have evolved over the last several years....
Verilog — A Tutorial Introduction.- Logic Synthesis.- Behavioral Modeling.- Concurrent Processes.- Module Hierarchy.- Logic Level Modeling.- Cycle-Accurate Specification.- Advanced Timing.- User-Defined Primitives.- Switch Level Modeling.- Projects.