Verilog HDL: A Guide to Digital Design and Synthesis / Edition 1

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Overview

Verilog HDL is a language for digital design, just as C is a language for programming. This complete Verilog HDL reference progresses from the basic Verilog concepts to the most advanced concepts in digital design. KEY TOPICS: Covers the gamut of Verilog HDL fundamentals, such as gate, RTL, and behavioral modeling, all the way to advanced concepts, such as timing simulation, switch level modeling, PLI, and logic synthesis. For Verilog HDL digital IC and system design professionals.


'Still going' may sound like the commercial for Energizer batteries, however, in this case, the statement is true. Verilog HDL continues to prove its excellence in teaching Verilog hardware description language like no other book on the topic. Although it is intended for beginners and intermediate users, advanced users can use this book in conjunction with the manuals and training materials for Verilog-based products. Due to its extensive use in the design of integrated circuit chips and digital systems, Verilog has become an industry standard over the last few years.

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Editorial Reviews

From Barnes & Noble

Fatbrain Review

'Still going' may sound like the commercial for Energizer batteries, however, in this case, the statement is true. Verilog HDL continues to prove its excellence in teaching Verilog hardware description language like no other book on the topic. Although it is intended for beginners and intermediate users, advanced users can use this book in conjunction with the manuals and training materials for Verilog-based products. Due to its extensive use in the design of integrated circuit chips and digital systems, Verilog has become an industry standard over the last few years.

This book gives a broad overview of Verilog-based topics, emphasizing practical design and synthesis, and complies with the IEEE 1364 Verilog HDL standard. Part 1 describes basic Verilog issues, and covers digital design principles with Verilog, design methodologies, lexical conventions, modules and ports, and related topics. Gate-level modeling is addressed before behavioral modeling so that a new user can easily move to higher levels of abstraction such as data flow and behavioral modeling.

Part 2 covers advanced topics in Verilog, including timing simulation, switch-level modeling, UPDs, PLI, and logic synthesis. The appendices constitute Part 3 of the book, and contain useful reference information such as strength-level modeling, a list of PLI routines, keywords, system tasks, compiler directives, formal syntax definition, Verilog tidbits, and large Verilog examples.

The book includes over 300 illustrations, exercises, and examples, and a Verilog Internet reference resource list. The chapters are furnished with objectives and summaries. The companion CD-ROM containsa Verilog simulator with a graphical user interface and the source code from the book.

Booknews
More concerned with the practical requirements of designing digital integrated-circuit chips than with the hardware description language that is increasingly being used for the job. Suitable as a text for a one-semester logic design course based on Verilog-HDL; and as a quick reference for advanced users. Includes a CD for Windows. No bibliography. Annotation c. Book News, Inc., Portland, OR (booknews.com)
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Product Details

  • ISBN-13: 9780134516752
  • Publisher: Prentice Hall Professional Technical Reference
  • Publication date: 2/12/1996
  • Edition description: Book and CD-ROM
  • Edition number: 1
  • Pages: 396
  • Product dimensions: 7.13 (w) x 9.48 (h) x 0.98 (d)

Meet the Author


Samir Palnitkar is a leading authority on Verilog HDL, modeling, verification, logic synthesis and EDA-based methodologies in digital design. He is currently the president of Indus Consulting Services, Inc., a company which offers specialized services for design and verification of micrprocessors, ASICs and systems. Previously, he was a member of the technical staff in the microprocessor design group at Sun Microsystems, Inc. in Sunnyvale, CA. He holds a Bachelor of Technology in Electrical Engineering from Indian Institute of Technology, Kanpur, a Master's in Electrical Engineering from University of Washington, Seattle and is currently pursuing an MBA degree at San Jose State University, San Jose, CA.

Mr. Palnitkar has worked extensively with design and verification on various successful microprocessor, ASIC and system projects. He was the lead developer of the Verilog framework for the shared memory, cache coherent, multiprocessor architecture, popularly known as the UltraSPARC Port Architecture, defined for Sun's next generation UltraSPARC-based desktop systems. Besides the UltraSPARC CPU, he was involved in the development of I/O, graphics, system controller and discrete cosine transform ASICs. Mr. Palnitkar was also a leading member of the group that first experimented with cycle simulation technology on joint projects with simulator companies. He has extensive experience with a variety of EDA tools such as Verilog-XL, Chronologic VCS, Speedsim, Synopsys, Pearl, Motive, Magellan, Signalscan, ATT Design System and Design Data Management Systems.

He is the author of two US patents pending approval, one for a novel method to analyze finite state machines andthe other for work on cycle simulation technology. He has also published several technical papers. In his spare time, Mr. Palnitkar likes to play cricket and tennis.

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Read an Excerpt

During my earliest experience with Verilog HDL, I was looking for a book that could give me a "jump start" on using Verilog HDL. I wanted to learn basic digital design paradigms and the necessary Verilog HDL constructs that would help me build small digital circuits, using Verilog and run simulations. After I had gained some experience with building basic Verilog models, I wanted to learn to use Verilog HDL to build larger designs. At that time I was searching for a book that broadly discussed advanced Verilog-based digital design concepts and real digital design methodologies. Finally, when I had gained enough experience with digital design and verification of real IC chips, though manuals of Verilog-based products were available, from time to time, I felt the need for a Verilog HDL book that would act as a handy reference. This book emphasizes breadth rather than depth. The book imparts to the reader a working knowledge of a broad variety of Verilog-based topics, thus giving the reader a global understanding of Verilog HDL-based design. The book leaves the in-depth coverage of each topic to the Verilog HDL language reference manual and the reference manuals of the individual Verilog-based products. This book should be classified not only as a Verilog HDL book but, more generally, as a digital design book. It important to realize that Verilog HDL is only a tool used in digital design. It is the means to an end- the digital IC chip. Therefore, this book stresses the practical design perspective more than the mere language aspects of Verilog HDL. With HDL-based digital design becoming popular, no digital designer can afford to ignore HDLs.

Who Should Use This Book...
Thebook is intended primarily for beginners and intermediate-level Verilog users. However, for advanced Verilog users, the broad coverage of topics makes it an excellent reference book to be used in conjunction with the manuals and training materials of Verilog-based products. The book presents a logical progression of Verilog HDL-based topics. It starts with the basics, such as HDL-based design methodologies, and then gradually builds on the basics to eventually reach advanced topics, such as PLI or logic synthesis. Thus, the book is useful to Verilog users with varying levels of expertise as explained below.

Students in logic design courses at universities Part 1 of this book is ideal for a foundation semester course in Verilog HDL-based logic design. Students are exposed to hierarchical modeling concepts, basic Verilog constructs and modeling techniques, and the necessary knowledge to write small models and run simulations. New Verilog users in the industry Companies are moving to Verilog HDL- based design. Part 1 of this book is a perfect jump start for designers who want to orient their skills toward HDL-based design. Users with basic Verilog knowledge who need to understand advanced concepts Part 2 of this book discusses advanced concepts, such as UDPs, timing simulation, PLI, and logic synthesis, which are necessary for graduation from small Verilog models to larger designs. Verilog experts

All Verilog topics are covered, from the basics modeling constructs to advanced topics like PLIs and logic synthesis. For Verilog experts, this book is a handy reference to be used along with the reference manuals. The material in the book sometimes leans toward an Application Specific Integrated Circuit (ASIC) design methodology. However, the concepts explained in the book are general enough to be applicable to the design of FPGAs, PALs, buses, boards, and systems. The book uses Medium Scale Integration (MSI) logic examples to simplify discussion. The same concepts apply to VLSI designs.

How This Book Is Organized:
This book is organized into three parts. Part 1, Basic Verilog Topics, covers all information that a new user needs to build small Verilog models and run simulations. Note that in Part 1, gate-level modeling is addressed before behavioral modeling. I have chosen to do so because I think that it is easier for a new user to see a 1-1 correspondence between gate- level circuits and equivalent Verilog descriptions. Once gate-level modeling is understood, a new user can move to higher levels of abstraction, like data flow modeling and behavioral modeling, without losing sight of the fact that Verilog HDL is a language for digital design and is not a programming language. Thus, a new user starts off with the idea that Verilog is a language for digital design. New users who start with behavioral modeling often tend to write Verilog the way they write their C programs. They sometimes lose sight of the fact that they are trying to represent hardware circuits by using Verilog. Part 1 contains nine chapters.

Part 2, Advanced Verilog Topics, contains the advanced concepts a Verilog user needs to know to graduate from small Verilog models to larger designs. Advanced topics such as timing simulation, switch-level modeling, UDPs, PLI, and logic synthesis are covered. Part 2 contains five chapters. Part 3, Appendices, contains information useful as a reference. Useful information, such as strength-level modeling, list of PLI routines, formal syntax definition, Verilog tidbits, and large Verilog examples is included. Part 3 contains six appendices.

Conventions Used in This Book. Table\x11PR-1 describes the type changes and symbols used in this book. Table\x11PR-1 Typographic Conventions Typeface or Symbol
Description
Examples: AaBbCc123 Keywords, system tasks and compiler directives that are a part of Verilog HDL and, nand, $display, `define AaBbCc123 Emphasis. cell characterization, instantiation AaBbCc123 Names of signals, modules, ports, etc. fulladd4, D_FF, out A few other conventions need to be clarified.

In the book, use of Verilog and Verilog HDL refers to the "Verilog Hardware Description Language." Any reference to a Verilog-based simulator is specifically mentioned, using words such as Verilog simulator or trademarks such as Verilog-XL or VCS.

The word designer is used frequently in the book to emphasize the digital design perspective. However, it is a general term used to refer to a Verilog HDL user.
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Table of Contents

About the Author
Foreword
Preface
Acknowledgments
1 Overview of Digital Design with Verilog HDL 3
2 Hierarchical Modeling Concepts 11
3 Basic Concepts 27
4 Modules and Ports 47
5 Gate-Level Modeling 61
6 Dataflow Modeling 85
7 Behavioral Modeling 115
8 Tasks and Functions 157
9 Useful Modeling Techniques 169
10 Timing and Delays 193
11 Switch-Level Modeling 213
12 User-Defined Primitives 229
13 Programming Language Interface 249
14 Logic Synthesis with Verilog HDL 275
A. Strength Modeling and Advanced Net Definitions 321
B. List of PLI Routines 327
C. List of Keywords, System Tasks, and Compiler Directives 343
D. Formal Syntax Definition 345
E. Verilog Tidbits 363
F. Verilog Examples 367
Bibliography 381
Index 383
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Preface

During my earliest experience with Verilog HDL, I was looking for a book that could give me a "jump start" on using Verilog HDL. I wanted to learn basic digital design paradigms and the necessary Verilog HDL constructs that would help me build small digital circuits, using Verilog and run simulations. After I had gained some experience with building basic Verilog models, I wanted to learn to use Verilog HDL to build larger designs. At that time I was searching for a book that broadly discussed advanced Verilog-based digital design concepts and real digital design methodologies. Finally, when I had gained enough experience with digital design and verification of real IC chips, though manuals of Verilog-based products were available, from time to time, I felt the need for a Verilog HDL book that would act as a handy reference. This book emphasizes breadth rather than depth. The book imparts to the reader a working knowledge of a broad variety of Verilog-based topics, thus giving the reader a global understanding of Verilog HDL-based design. The book leaves the in-depth coverage of each topic to the Verilog HDL language reference manual and the reference manuals of the individual Verilog-based products. This book should be classified not only as a Verilog HDL book but, more generally, as a digital design book. It important to realize that Verilog HDL is only a tool used in digital design. It is the means to an end- the digital IC chip. Therefore, this book stresses the practical design perspective more than the mere language aspects of Verilog HDL. With HDL-based digital design becoming popular, no digital designer can afford to ignore HDLs.

Who Should Use This Book...
Thebook is intended primarily for beginners and intermediate-level Verilog users. However, for advanced Verilog users, the broad coverage of topics makes it an excellent reference book to be used in conjunction with the manuals and training materials of Verilog-based products. The book presents a logical progression of Verilog HDL-based topics. It starts with the basics, such as HDL-based design methodologies, and then gradually builds on the basics to eventually reach advanced topics, such as PLI or logic synthesis. Thus, the book is useful to Verilog users with varying levels of expertise as explained below.

Students in logic design courses at universities Part 1 of this book is ideal for a foundation semester course in Verilog HDL-based logic design. Students are exposed to hierarchical modeling concepts, basic Verilog constructs and modeling techniques, and the necessary knowledge to write small models and run simulations. New Verilog users in the industry Companies are moving to Verilog HDL- based design. Part 1 of this book is a perfect jump start for designers who want to orient their skills toward HDL-based design. Users with basic Verilog knowledge who need to understand advanced concepts Part 2 of this book discusses advanced concepts, such as UDPs, timing simulation, PLI, and logic synthesis, which are necessary for graduation from small Verilog models to larger designs. Verilog experts

All Verilog topics are covered, from the basics modeling constructs to advanced topics like PLIs and logic synthesis. For Verilog experts, this book is a handy reference to be used along with the reference manuals. The material in the book sometimes leans toward an Application Specific Integrated Circuit (ASIC) design methodology. However, the concepts explained in the book are general enough to be applicable to the design of FPGAs, PALs, buses, boards, and systems. The book uses Medium Scale Integration (MSI) logic examples to simplify discussion. The same concepts apply to VLSI designs.

How This Book Is Organized:
This book is organized into three parts. Part 1, Basic Verilog Topics, covers all information that a new user needs to build small Verilog models and run simulations. Note that in Part 1, gate-level modeling is addressed before behavioral modeling. I have chosen to do so because I think that it is easier for a new user to see a 1-1 correspondence between gate- level circuits and equivalent Verilog descriptions. Once gate-level modeling is understood, a new user can move to higher levels of abstraction, like data flow modeling and behavioral modeling, without losing sight of the fact that Verilog HDL is a language for digital design and is not a programming language. Thus, a new user starts off with the idea that Verilog is a language for digital design. New users who start with behavioral modeling often tend to write Verilog the way they write their C programs. They sometimes lose sight of the fact that they are trying to represent hardware circuits by using Verilog. Part 1 contains nine chapters.

Part 2, Advanced Verilog Topics, contains the advanced concepts a Verilog user needs to know to graduate from small Verilog models to larger designs. Advanced topics such as timing simulation, switch-level modeling, UDPs, PLI, and logic synthesis are covered. Part 2 contains five chapters. Part 3, Appendices, contains information useful as a reference. Useful information, such as strength-level modeling, list of PLI routines, formal syntax definition, Verilog tidbits, and large Verilog examples is included. Part 3 contains six appendices.

Conventions Used in This Book. Table\x11PR-1 describes the type changes and symbols used in this book. Table\x11PR-1 Typographic Conventions Typeface or Symbol
Description
Examples: AaBbCc123 Keywords, system tasks and compiler directives that are a part of Verilog HDL and, nand, $display, 'define AaBbCc123 Emphasis. cell characterization, instantiation AaBbCc123 Names of signals, modules, ports, etc. fulladd4, D_FF, out A few other conventions need to be clarified.

In the book, use of Verilog and Verilog HDL refers to the "Verilog Hardware Description Language." Any reference to a Verilog-based simulator is specifically mentioned, using words such as Verilog simulator or trademarks such as Verilog-XL or VCS.

The word designer is used frequently in the book to emphasize the digital design perspective. However, it is a general term used to refer to a Verilog HDL user.
Read More Show Less

Foreword

From a modest beginning in early 1984 at Gateway Design Automation, the Verilog hardware description language has become an industry standard as a result of extensive use in design of integrated circuit chips and digital systems. Verilog came into being as a proprietary language supported by a simulation environment that was the first to support mixed-level design representations comprising switches, gates, RTL, and higher levels of abstractions of digital circuits. The simulation environment provided a powerful and uniform method to express digital designs as well as tests that were meant to verify such designs.

There were three key factors that drove the acceptance and dominance of Verilog in the marketplace. First, the introduction of the Programming Language Interface (PLI) permitted users of Verilog to literally extend and customize the simulation environment. Since then, users have exploited the PLI and their success at adapting Verilog to their environment has been a real winner for Verilog. The second key factor which drove Verilog's dominance came from Gateway paying close attention to the needs of the ASIC foundries and enhancing Verilog in close partnership with Motorola, National, and UTMC in the 1987-1989 time-frame. The realization that the vast majority of logic simulation was being done by designers of ASIC chips drove this effort. With ASIC foundries blessing the use of Verilog and even adopting it as their internal sign-off simulator, the industry acceptance of Verilog was driven even further. The third and final key factor behind the success of Verilog was the introduction of Verilog based synthesis technology by Synopsys in 1987. Gateway licensed itsproprietary Verilog language to Synopsys for this purpose. The combination of the simulation and synthesis technologies served to make Verilog the language of choice for the hardware designers. The arrival of the VHDL (VHSIC Hardware Description Language), along with the powerful alignment of the remaining EDA vendors driving VHDL as an IEEE standard, led to the placement of Verilog in the public domain. Today, Verilog has become a widely used language and is on its way to becoming an IEEE Standard.

There are several Verilog based text books available to the hardware designer. Samir's book is an excellent guide to the user of the Verilog language. Not only does it explain the language constructs with a rich variety of examples, it also goes into details of the usage of the PLI and application of the synthesis technology. Verilog provides powerful constructs that enable more accurate modelling and simulation of the ASIC building blocks or cells. Samir's book does a very job of describing how such modelling can be carried out through specification of timing and logic behavior of such cells.

I can still remember the challenges of teaching Verilog and its associated methodologies to designers who were set in the ways of gate level design. By using Samir's book, beginning users of Verilog will become productive sooner, and experienced Verilog users will get the latest in a convenient reference book that can refresh their understanding of Verilog.

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  • Anonymous

    Posted April 17, 2000

    Caution: CDROM

    The book was informative but the Verilog simulator supplied on the CDROM crashes NT4.0

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