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VHDL Answers to Frequently Asked Questions / Edition 2

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This book addresses: misinterpretations in the use of the language (VHDL); methods for writing error free, and simulation efficient, code for testbench designs and for synthesis; and general principles and guidelines for design verification.
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Editorial Reviews

A follow-up to the author's book "VHDL Coding Styles and Methodologies", this volume provides engineers and students with important tools for improving proficiency in VHDL. The book is organized into nine sections, starting with language- related issues and progressing to real applications of VHDL. Sections include language elements, arrays, drivers, subprograms, packages, models, synthesis, design verification and testbench, and miscellaneous issues. Throughout, complete examples are used to demonstrate problems and solutions. All VHDL code described in the book is on the companion 3.5<"> PC disk. Annotation c. by Book News, Inc., Portland, Or.
This book is intended for engineers and students who seek proficiency in VHDL. It includes packages of common utilities that are useful in the generation of debug code and testbench designs and contains many complete and useful examples that can be compiled and simulated. Chapter topics include language elements, arrays, drivers, subprograms, packages, models, synthesis, design verification and design for reuse<-->which defines coding and design techniques that are independent of technological advances and is new to this second edition. A diskette contains all the book examples and other useful reference material. Annotation c. by Book News, Inc., Portland, Or.
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Product Details

  • ISBN-13: 9780792381150
  • Publisher: Springer US
  • Publication date: 1/1/1998
  • Edition description: 2nd ed. 1998
  • Edition number: 2
  • Pages: 384
  • Product dimensions: 0.94 (w) x 10.00 (h) x 7.00 (d)

Table of Contents

Preface. About the Disk. Notation Conventions: Symbols. Syntactic Description. 1. Language Elements. 2. Arrays. 3. Drivers. 4. Subprograms. 5. Packages. 6. Models. 7. Synthesis. 8. Design Verification and Testbench. 9. Potpourri. 10. Design for Reuse. Appendices: A. VHDL'93 and VHDL'87 Syntax Summary. B. Package STANDARD. C. Package TEXTIO. D. Package STD_LOGIC_1164. E. Package STD_LOGIC_ARITH. F. VHDL Predefined Attributes. Bibliography. Index.
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