VHDL Answers to Frequently Asked Questions

Overview

VHDL Answers to Frequently Asked Questions is a follow-up to the author's book VHDL Coding Styles and Methodologies (ISBN 0-7923-9598-0). On completion of his first book, the author continued teaching VHDL and actively participated in the comp.lang.vhdl newsgroup. During his experiences, he was enlightened by the many interesting issues and questions relating to VHDL and synthesis. These pertained to: misinterpretations in the use of the language; methods for writing error-free, and simulation-efficient, code for...

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Overview

VHDL Answers to Frequently Asked Questions is a follow-up to the author's book VHDL Coding Styles and Methodologies (ISBN 0-7923-9598-0). On completion of his first book, the author continued teaching VHDL and actively participated in the comp.lang.vhdl newsgroup. During his experiences, he was enlightened by the many interesting issues and questions relating to VHDL and synthesis. These pertained to: misinterpretations in the use of the language; methods for writing error-free, and simulation-efficient, code for testbench designs and for synthesis; and general principles and guidelines for design verification. As a result of this wealth of public knowledge contributed by a large VHDL community, the author decided to act as a facilitator of this information by collecting different classes of VHDL issues, and by elaborating on these topics through complex simulatable examples. This book is intended for those who are seeking an enhanced proficiency in VHDL.
This book differs from other VHDL books in many respects. This book:

• emphasizes real VHDL, rather than philosophical or introductory types of information
• emphasizes application of VHDL for synthesis
• uses complete examples to demonstrate problems and solutions
• provides a disk that includes all the book examples and other useful reference VHDL material
• uses easy to remember symbology notation to emphasize language rules, good and poor methodology and coding styles
• identifies obsolete VHDL constructs that must be avoided
• identifies synthesizable/non-synthesizable structures
• uses a question and answer format to clarify and emphasize the concerns of VHDL users.

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Editorial Reviews

Booknews
This book is intended for engineers and students who seek proficiency in VHDL. It includes packages of common utilities that are useful in the generation of debug code and testbench designs and contains many complete and useful examples that can be compiled and simulated. Chapter topics include language elements, arrays, drivers, subprograms, packages, models, synthesis, design verification and design for reuse<-->which defines coding and design techniques that are independent of technological advances and is new to this second edition. A diskette contains all the book examples and other useful reference material. Annotation c. by Book News, Inc., Portland, Or.
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Product Details

  • ISBN-13: 9781475726268
  • Publisher: Springer US
  • Publication date: 10/28/2013
  • Edition description: Softcover reprint of the original 1st ed. 1997
  • Pages: 291
  • Product dimensions: 7.00 (w) x 10.00 (h) x 0.67 (d)

Table of Contents

Preface. About the Disk. Notation Conventions. 1. Language Elements. 2. Arrays. 3. Drivers. 4. Subprograms. 5. Packages. 6. Models. 7. Synthesis. 8. Design Verification and Testbench. 9. Potpourri. Appendix A: VHDL'93 and VHDL'87 Syntax Summary. Appendix B: Package Standard. Appendix C: Package TEXTIO. Appendix D: Package STD_LOGIC_1164. Appendix E: Package STD_LOGIC_ARITH. Appendix F: VHDL Predefined Attributes. Bibliography. Index.

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