VHDL Designer's Reference / Edition 1

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VHDL is the most widespread standard for hardware description. From its initial applications in simulation and ASIC description, VHDL is now being used in a wide range of applications at all levels, from system down to gate. The applications, which include synthesis and formal proof, make VHDL a design support tool as well as a deliverable.
The use of VHDL implies a new approach to design. The VHDL Designer's Reference offers engineers and students practical help in addressing real problems encountered when implementing and using VHDL in their companies or research laboratories. It is thus a valuable reference for all practising designers.
Intended for the experienced designer, VHDL Designer's Reference discusses modeling issues, design methods, efficiency tricks and portability traps. It also compares VHDL with other hardware description languages such as M, Verilog, and UDL/I. This complete reference provides a resource to help improve the designer's use of VHDL.

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Editorial Reviews

VDHL is the most widespread hardware description language supported by CAD vendors. The language is terse and difficult to use. This first- rate reference will help programmers answer these questions about VDHL: why choose VDHL, which VDHL tools should be chosen, which modeling methodology should be adopted, how should the VDHL environment be customized, and what are the tricks and traps? Annotation c. Book News, Inc., Portland, OR (booknews.com)
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Product Details

  • ISBN-13: 9780792317562
  • Publisher: Springer US
  • Publication date: 5/21/1992
  • Edition description: 1992
  • Edition number: 1
  • Pages: 455
  • Product dimensions: 1.13 (w) x 6.14 (h) x 9.21 (d)

Table of Contents

1. Introduction. 2. VHDL Tools. 3. VHDL and Modeling Issues. 4. Structuring the Environment. 5. System Modeling. 6. Structuring Methodology. 7. Tricks and Traps. 8. M and VHDL. 9. VERILOG and VHDL. 10. UDL/I and VHDL. 11. Memo. 12. Index. List of Figures.
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