VHDL / Edition 3

VHDL / Edition 3

by Douglas L. Perry
     
 

ISBN-10: 0070494363

ISBN-13: 9780070494367

Pub. Date: 04/28/1998

Publisher: McGraw-Hill Companies, The


* Teaches VHDL by example
* Includes tools for simulation and synthesis
* CD-ROM containing Code/Design examples and a working demo of ModelSIM

THE HANDS-DOWN FAVORITE USER'S GUIDE TO VHDLCOMPLETELY UPDATED TO REFLECT THE VERY LATEST DESIGN METHODS

CD-ROM WITH WORKING CODE EXAMPLES, VERIFICATION TOOLS AND MORE

No matter what your

Overview


* Teaches VHDL by example
* Includes tools for simulation and synthesis
* CD-ROM containing Code/Design examples and a working demo of ModelSIM

THE HANDS-DOWN FAVORITE USER'S GUIDE TO VHDLCOMPLETELY UPDATED TO REFLECT THE VERY LATEST DESIGN METHODS

CD-ROM WITH WORKING CODE EXAMPLES, VERIFICATION TOOLS AND MORE

No matter what your current level of expertise, nothing will have you writing and verifying concise, efficient VHDL descriptions of hardware designs as fast – or as painlessly – as this classic tutorial from master teacher Doug Perry. Beginners will find it an invaluable learning tool and experienced pros will keep it on their desk as a trusted reference.

Perry teaches VHDL through a series of hundreds of practical, detailed examples, gradually increasing in complexity until you're capable of designing a fully functional CPU. The new Fourth Edition has been completely updated with all of the VDHL codes used in the examples changed to reflect today's faster and more efficient design methods. You'll also find:


* A CD-ROM containing working code of all of the VDHL examples, with their matching designs along with VITAL verification tools and a working copy of ModelSIM
* All the tools you need for simulation and synthesis
* A listing of the IEEE 1164 STD-LOGIC package used throughout the book
* Useful tables and figures
* Instructions for reading the Bachus-Naur format (BNF) descriptions found in the VHDL Language Reference Manual

There truly is no faster or smarter way to master VHDL than Doug Perry's “learn by example” approach. It works!

Product Details

ISBN-13:
9780070494367
Publisher:
McGraw-Hill Companies, The
Publication date:
04/28/1998
Edition description:
Older Edition
Pages:
493
Product dimensions:
7.72(w) x 9.56(h) x 1.59(d)

Table of Contents

Preface xv
Chapter 1 Introduction to VHDL
1(16)
VHSIC Program
2(1)
VHDL as a Standard
2(1)
Learning VHDL
3(1)
VHDL Terms
3(1)
Traditional Design Methods
4(13)
Traditional Schematics
6(1)
Symbols Versus Entities
7(1)
Schematics Versus Architectures
7(1)
Component Instantiation
8(1)
Behavioral Descriptions
9(1)
Concurrent Signal Assignment
10(1)
Event Scheduling
11(1)
Statement Concurrency
11(1)
Sequential Behavior
12(1)
Process Statements
12(1)
Process Declarative Region
13(1)
Process Statement Part
13(1)
Process Execution
13(1)
Sequential Statements
14(1)
Architecture Selection
14(1)
Configuration Statements
15(1)
Power of Configurations
15(2)
Chapter 2 Behavioral Modeling
17(24)
Introduction to Behavioral Modeling
18(4)
Transport Versus Inertial Delay
22(3)
Inertial Delay
22(1)
Transport Delay
23(1)
Inertial Delay Model
24(1)
Transport Delay Model
25(1)
Simulation Deltas
25(4)
Drivers
29(2)
Driver Creation
29(1)
Bad Multiple Driver Model
30(1)
Generics
31(2)
Block Statements
33(8)
Guarded Blocks
37(4)
Chapter 3 Sequential Processing
41(34)
Process Statement
42(2)
Sensitivity List
42(1)
Process Example
42(2)
Signal Assignment Versus Variable Assignment
44(4)
Incorrect Mux Example
45(2)
Correct Mux Example
47(1)
Sequential Statements
48(1)
IF Statements
49(1)
CASE Statements
50(2)
LOOP Statements
52(4)
NEXT Statements
55(1)
EXIT Statement
56(2)
ASSERT Statement
58(3)
Assertion BNF
59(2)
WAIT Statements
61(8)
WAIT ON Signal
64(1)
WAIT UNTIL Expression
64(1)
WAIT FOR time expression
64(1)
Multiple WAIT Conditions
65(1)
WAIT Time-Out
66(2)
Sensitivity List Versus WAIT Statement
68(1)
Concurrent Assignment Problem
69(3)
Passive Processes
72(3)
Chapter 4 Data Types
75(36)
Object Types
76(4)
Signal
76(2)
Variables
78(1)
Constants
79(1)
Data Types
80(27)
Scalar Types
81(7)
Composite Types
88(2)
Incomplete Types
100(4)
File Types
104(3)
File Type Caveats
107(1)
Subtypes
107(4)
Chapter 5 Subprograms and Packages
111(34)
Subprograms
112(25)
Function
112(3)
Conversion Functions
115(6)
Resolution Functions
121(14)
Procedures
135(2)
Packages
137(8)
Package Declaration
138(1)
Deferred Constants
138(1)
Subprogram Declaration
139(1)
Package Body
140(5)
Chapter 6 Predefined Attributes
145(30)
Value Kind Attributes
146(7)
Value Type Attributes
146(3)
Value Array Attributes
149(2)
Value Block Attributes
151(2)
Function Kind Attributes
153(9)
Function Type Attributes
153(3)
Function Array Attributes
156(2)
Function Signal Attributes
158(1)
Attributes 'EVENT and 'LAST_VALUE
159(1)
Attribute 'LAST_EVENT
160(2)
Attribute 'ACTIVE and 'LAST_ACTIVE
162(1)
Signal Kind Attributes
162(9)
Attribute 'DELAYED
163(3)
Attribute 'STABLE
166(2)
Attribute 'QUIET
168(2)
Attribute 'TRANSACTION
170(1)
Type Kind Attributes
171(1)
Range Kind Attributes
172(3)
Chapter 7 Configurations
175(36)
Default Configurations
176(2)
Component Configurations
178(7)
Lower-Level Configurations
181(1)
Entity-Architecture Pair Configuration
182(1)
Port Maps
183(2)
Mapping Library Entities
185(4)
Generics in Configurations
189(3)
Generic Value Specification in Architecture
192(3)
Generic Specifications in Configurations
195(5)
Board-Socket-Chip Analogy
200(4)
Block Configurations
204(2)
Architecture Configurations
206(5)
Chapter 8 Advanced Topics
211(26)
Overloading
212(9)
Subprogram Overloading
212(5)
Overloading Operators
217(4)
Aliases
221(1)
Qualified Expressions
222(2)
User-Defined Attributes
224(2)
Generate Statements
226(5)
Irregular Generate Statement
228(3)
TextIO
231(6)
Chapter 9 Synthesis
237(20)
Register Transfer Level Description
238(5)
Constraints
243(2)
Timing Constraints
244(1)
Clock Constraints
244(1)
Attributes
245(2)
Load
246(1)
Drive
246(1)
Arrival Time
246(1)
Technology Libraries
247(2)
Synthesis
249(8)
Translation
249(1)
Boolean Optimization
250(1)
Flattening
251(1)
Factoring
252(1)
Mapping to Gates
253(4)
Chapter 10 VHDL Synthesis
257(24)
Simple Gate--Concurrent Assignment
258(1)
IF Control Flow Statements
259(3)
Case Control Flow Statements
262(1)
Simple Sequential Statements
263(3)
Asynchronous Reset
266(1)
Asynchronous Preset and Clear
267(2)
More Complex Sequential Statements
269(4)
Four-Bit Shifter
270(3)
State Machine Example
273(8)
Chapter 11 High Level Design Flow
281(16)
RTL Simulation
283(2)
VHDL Synthesis
285(6)
Functional Gate Level Verification
291(1)
Place and Route
292(2)
Post Layout Timing Simulation
294(1)
Static Timing
295(2)
Chapter 12 Top-Level System Design
297(14)
CPU Design
298(1)
Top-Level System Operation
298(1)
Instructions
299(1)
Sample Instruction Representation
300(1)
CPU Top-Level Design
301(10)
Block Copy Operation
307(4)
Chapter 13 CPU: Synthesis Description
311(26)
ALU
314(3)
Comp
317(2)
Control
319(10)
Reg
329(1)
Regarray
330(2)
Shift
332(2)
Trireg
334(3)
Chapter 14 CPU: RTL Simulation
337(28)
Testbenches
338(19)
Kinds of Testbenches
339(2)
Stimulus Only
341(4)
Full Testbench
345(3)
Simulator Specific
348(2)
Hybrid Testbenches
350(3)
Fast Testbench
353(4)
CPU Simulation
357(8)
Chapter 15 CPU Design: Synthesis Results
365(20)
Control
368(2)
Alu
370(2)
Comp
372(2)
Reg
374(2)
Regarray
376(2)
Shift
378(2)
Trireg
380(5)
Chapter 16 Place and Route
385(10)
Place and Route Process
386(3)
Placing and Routing the Device
389(6)
Setting up a project
389(3)
Reading in the Netlist and Performing Place and Route
392(1)
Analyzing the Results
392(3)
Chapter 17 CPU: VITAL Simulation
395(20)
VITAL Library
397(1)
VITAL Simulation Process Overview
398(1)
VITAL Implementation
398(1)
Simple VITAL Model
399(3)
VITAL Architecture
402(6)
Wire Delay Section
402(2)
Flip-Flop Example
404(4)
SDF File
408(5)
VITAL Simulation
410(3)
Back-Annotated Simulation
413(2)
Appendix A Standard Logic Package
415(22)
Appendix B VHDL Reference Tables
437(10)
Appendix C Reading VHDL BNF
447(4)
Appendix D VHDL93 Updates
451(20)
Alias
451(1)
Attribute Changes
452(2)
Bit String Literal
454(1)
DELAY_LENGTH Subtype
454(1)
Direct Instantiation
454(1)
Extended Identifiers
455(1)
File Operations
456(1)
Foreign Interface
457(1)
Generate Statement Changes
458(1)
Globally Static Assignment
458(1)
Groups
459(1)
Incremental Binding
460(1)
Postponed Process
461(1)
Pure and Impure Functions
462(1)
Pulse Reject
462(1)
Report Statement
463(1)
Shared Variables
463(2)
Shift Operators
465(1)
SLL--shift left logical
465(1)
SRL--shift right logical
465(1)
SLA--shift left arithmetic
465(1)
SRA--shift right arithmetic
465(1)
ROL--rotate left
466(1)
ROR--rotate right
466(1)
Syntax Consistency
466(2)
Unaffected
468(1)
XNOR Operator
468(3)
Index 471

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