VHDL: Hardware Description and Design / Edition 1

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Editorial Reviews

A working reference for hardware designers. Includes complete examples used to illustrate features of VHDL language and provides insight into particular classes of hardware devices modelled in VHDL. Annotation c. Book News, Inc., Portland, OR booknews.com
From the Publisher
'... this is a most useful publication.'
Journal of Semicustom ICs 8 (3) 1991
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Product Details

  • ISBN-13: 9780792390305
  • Publisher: Springer US
  • Publication date: 6/30/1989
  • Edition description: 1989
  • Edition number: 1
  • Pages: 299
  • Product dimensions: 0.81 (w) x 9.21 (h) x 6.14 (d)

Table of Contents

1 — Introduction.- Why VHDL.- Terminology and Conventions.- 2 — A Model of Hardware.- A Model of Behavior.- A Model of Time.- A Model of Structure.- 3 — Basics.- Structure and Behavior.- Data Types and Objects.- Data Types.- Objects.- Hooking Constructs Together.- Interface Lists.- Association Lists.- Major VHDL Constructs.- Entity Declarations.- Architecture Bodies.- Subprograms.- Packages and Use Clauses.- Libraries.- Library Units and Order of Analysis.- Visibility of a Primary Unit and Libraries.- 4 — Data Types.- Literals.- Scalar Types.- Composite Types.- Aggregates and String Literals.- Referencing Elements of Composites.- Subtypes.- Attributes.- Predefined Operators.- 5 — Behavioral Description.- Process Statements.- The Wait Statement: Activation and Suspension.- Behavioral Modeling — Sequential View.- Declarations.- Sequential Assignment.- Signal Assignment.- Signal Drivers.- Delay in Signal Assignments.- Variable Assignment.- Sequential Control.- Conditional Control.- Iterative Control.- Other Sequential Statements.- The Assertion Statement.- Procedure Calls.- The Return Statement.- The Null Statement.- Behavioral Modeling — Concurrent View.- Concurrent Statements and Equivalent Processes.- Concurrent Signal Assignment.- Concurrent Assertion Statement.- Resolved Signals.- A Counter Element.- 6 — Structural Description.- Basic Features of Structural Description.- Ports in Entity Declarations.- Port Modes and Direction of Data Flow.- Ports in Component Declarations.- Component Instantiation Statements.- Example: A Simple ALU.- Example: A Decoder.- Example: Data Bus.- Regular Structures.- Generate Statements.- Generics.- Configuration Specifications.- Default Values and Unconnected Ports.- Default Values.- Unconnected Ports.- 7 — Large Scale Design.- Managing Shared Designs.- Design Libraries and their Implementation.- Predefined Design Libraries.- The Use of Libraries for Revision Management.- Visibility and the Analysis Context.- Name Visibility in VHDL.- Access to External VHDL Libraries.- Partitioning a Design.- Concurrent and Sequential Procedure Calls.- The Block Statement.- Component Instantiations and Blocks.- Sharing Data Within a Design.- Specifying a Design Configuration.- How Component Binding Occurs.- Type Incompatibilities in Component Binding.- Mixing Structure and Behavior.- 8 — A Complete Example.- The Traffic Light Controller.- Creating the Specification.- Defining the System Types.- Creating the Interface.- The Body of the Specification.- Creating a Test Bench.- Partitioning the Design.- Choosing a Type Representation.- Revising the Specification.- The First Partition.- The Second Partition.- Starting the Implementation.- Setting Up the PLA.- 9 — Advanced Features.- Overloading.- Access Types.- File Types and I/O.- User-Defined Attributes.- Signal-Related Attributes.- Aliases.- Association by Subelement.- Guarded Assignment Statements.- Disconnection Specifications.- Null Transactions.- 10 — VHDL in Use.- A Device Controller.- Setup and Hold Timing.- A Neural Net.- A Systolic Array Multiplier.- Summary.- Appendix A — Predefined Environment261.- Reserved Words.- Attributes.- Type and Subtype Attributes.- Array Attributes.- Signal-Valued Attributes.- Signal-Related Attributes.- Packages.- The Package STANDARD.- The Package TEXTIO.- >Appendix B — VHDL Syntax.- >Appendix C — Suggested Reading.- >Index.

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