Vhdl: A Starter's Guide / Edition 2

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This handy reference gives readers a thorough grounding in the basic concepts and language of VHDL, and encourages them to apply what they have learned using realistic examples. Concepts are followed by examples and tutorials. Adds appendices to support material: Includes a tutorial for a popular VHDL simulator; a handy reference to common VHDL packages; and a detailed template for a VHDL model illustrating the relative ordering of program constructs. Emphasizes development of readers’ intuition and structured thinking about VHDL models without spending excessive time on advanced language features. Provides simulation and laboratory exercises that enable readers to quickly come up to speed in building useful, non-trivial models of digital systems. Provides tutorial descriptions and presentation of programming mechanics unique to CAD tools and environments. Includes examples, extensive use of timing diagrams, event lists and many tutorials for independent student study. Provides sample problems, many of which include worked solutions. Includes viewgraph masters and the VHDL source for all text examples. A useful reference for computer professionals who need to brush up on their VHDL knowledge.

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Product Details

  • ISBN-13: 9780131457355
  • Publisher: Prentice Hall
  • Publication date: 12/30/2004
  • Edition description: 2ND
  • Edition number: 2
  • Pages: 256
  • Sales rank: 850,156
  • Product dimensions: 6.90 (w) x 9.00 (h) x 0.70 (d)

Table of Contents

1. Introduction.

1.1 What is VHDL?

1.2 Digital System Design.

1.3 The Marketplace.

1.4 The Role of Hardware Description Languages.

1.5 Chapter Summary.

2. Modeling Digital Systems.

2.1 Motivation.

2.2 Describing Systems.

2.3 Events, Propagation Delays, and Concurrency.

2.4 Waveforms and Timing.

2.5 Signal Values.

2.6 Shared Signals.

2.7 Simulating Hardware Descriptions.

2.8 Chapter Summary.

3. Basic Language Concepts.

3.1 Signals.

3.2 Entity-Architecture.

3.3 Concurrent Statements.

3.4 Constructing VHDL Models Using CSAs.

3.5 Understanding Delays.

3.6 Chapter Summary.

4. Modeling Behaviors.

4.1 The Process Construct.

4.2 Programming Constructs.

4.3 More on Processes.

4.4 The Wait Statement.

4.5 Attributes.

4.6 Generating Clocks and Periodic Waveforms.

4.7 Using Signals in a Process.

4.8 Modeling State Machines.

4.9 Constructing VHDL Models Using Processes.

4.10 Common Programming Errors.

4.11 Chapter Summary.

5. Modeling Structure.

5.1 Describing Structure.

5.2 Constructing Structural VHDL Models.

5.3 Hierarchy, Abstraction, and Accuracy.

5.4 Generics.

5.5 The Generate Statement.

5.6 Configurations.

5.7 Common Programming Errors.

5.8 Chapter Summary.

6. Subprograms, Packages, and Libraries.

6.1 Essentials of Functions.

6.2 Essentials of Procedures.

6.3 Subprogram and Operator Overloading.

6.4 Essentials of Packages.

6.5 Essentials of Libraries.

6.6 Chapter Summary.

7. Basic Input/Output.

7.1 Basic Input/Output Operations.

7.2 The Package TEXTIO.

7.3 Testbenches in VHDL.

7.4 ASSERT Statement.

7.5 A Testbench Template.

7.6 Chapter Summary.

8. Simulation Mechanics.

8.1 Terminology and Directory Structure.

8.2 Simulation Steps.

8.3 Chapter Summary.

9. Identifiers, Data Types, and Operators.

9.1 Identifiers.

9.2 Data Objects.

9.3 Data Types.

9.4 Operators.

9.5 Chapter Summary.


Appendix A. Active-HDL Tutorial.

A.1 Using Active VHDL.

A.2 Miscellaneous Features.

A.3 Chapter Summary.

Appendix B. Standard VHDL Packages.

B.1 Package STANDARD.

B.2 Package TEXTIO.

B.3 The Standard Logic Package.

B.4 Other Useful Packages.

Appendix C. A Starting Program Template.

C.1 Construct Schematic.

C.2 Construct The Behavioral Model.


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