VLSI Circuit Design Methodology Demystified: A Conceptual Taxonomy / Edition 1

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This book was written to arm engineers qualified and knowledgeable in the area of VLSI circuits with the essential knowledge they need to get into this exciting field and to help those already in it achieve a higher level of proficiency. Few people truly understand how a large chip is developed, but an understanding of the whole process is necessary to appreciate the importance of each part of it and to understand the process from concept to silicon. It will teach readers how to become better engineers through a practical approach of diagnosing and attacking real-world problems.

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Product Details

  • ISBN-13: 9780470127421
  • Publisher: Wiley
  • Publication date: 11/16/2007
  • Edition number: 1
  • Pages: 224
  • Product dimensions: 6.16 (w) x 9.27 (h) x 0.57 (d)

Meet the Author

Liming Xiu is a Design Engineer and a Senior Member of Technical Staff (SMTS) at Texas Instruments, Inc. His interests include digital and mixed-signal integrated circuit design and VLSI physical design. He has worked on various mixed-signal devices, including video decoders, 3-D graphics controllers, and HDTV decoders, as physical design lead. He is also a Phase Lock Loop (PLL) expert. He is the inventor of "Flying-Adder" frequency and phase synthesis architecture, which has been used in many commercial products. He has eleven granted or pending U.S. patents. He is a Senior Member of the IEEE and the general chair of the IEEE Circuit and Systems Society, Dallas Chapter.

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Table of Contents

Foreword (Richard Templeton).

Foreword (Hans Stork).




1. What is a chip?

2. What are the requirements of a successful chip design?

3. What are the challenges in today’s very deep submicron (VDSM), multimillion gate designs?

4. What major process technologies are used in today’s design environment?

5. What are the goals of new chip design?

6. What are the major approaches of today’s very large scale integration (VLSI) circuit design practices?

7. What is standard cell-based, application-specific integrated circuit (ASIC) design methodology?

8. What is the system-on-chip (SoC) approach?

9. What are the driving forces behind the SoC trend?

10. What are the major tasks in developing a SoC chip from concept to silicon?

11. What are the major costs of developing a chip?


12. What are the major process steps in building MOSFET transistors?

13. What are the two types of MOSFET transistors?

14. What are base layers and metal layers?

15. What are wafers and dies?

16. What is semiconductor lithography?

17. What is a package?


18. What is the role of functional verification in the IC design process?

19. What are some of the design integrity issues?

20. What is design for testability?

21. Why is reducing the chip’s power consumption so important?

22. What are some of the challenges in chip packaging?

23. What are the advantages of design reuse?

24. What is hardware/software co-design?

25. Why is the clock so important?

26. What is the leakage current problem?

27. What is design for manufacturability?

28. What is chip reliability?

29. What is analog integration in the digital environment?

30. What is the role of EDA tools in IC design?

31. What is the role of the embedded processor in the SoC environment?


32. What are the major tasks and personnel required in a chip design project?

33. What are the major steps in ASIC chip construction?

34. What is the ASIC design flow?

35. What are the two major aspects of ASIC design flow?

36. What are the characteristics of good design flow?

37. What is the role of market research in an ASIC project?

38. What is the optimal solution of an ASIC project?

39. What is system-level study of a project?

40. What are the approaches for verifying design at the system level?

41. What is register-transfer-level (RTL) system-level description?

42. What are methods of verifying design at the register-transfer- level?

43. What is a test bench?

44. What is code coverage?

45. What is functional coverage?

46. What is bug rate convergence?

47. What is design planning?

48. What are hard macro and soft macro?

49. What is hardware description language (HDL)?

50. What is register-transfer-level (RTL) description of hardware?

51. What is standard cell? What are the differences among standard cell, gate-array, and sea-of-gate approaches?

52. What is an ASIC library?

53. What is logic synthesis?

54. What are the optimization targets of logic synthesis?

55. What is schematic or netlist?

56. What is the gate count of a design?

57. What is the purpose of test insertion during logic synthesis?

58. What is the most commonly used model in VLSI circuit testing?

59. What are controllability and observability in a digital circuit?

60. What is a testable circuit?

61. What is the aim of scan insertion?

62. What is fault coverage? What is defect part per million (DPPM)?

63. Why is design for testability important for a product’s financial success?

64. What is chip power usage analysis?

65. What are the major components of CMOS power consumption?

66. What is power optimization?

67. What is VLSI physical design?

68. What are the problems that make VLSI physical design so challenging?

69. What is floorplanning?

70. What is the placement process?

71. What is the routing process?

72. What is a power network?

73. What is clock distribution?

74. What are the key requirements for constructing a clock tree?

75. What is the difference between time skew and length skew in a clock tree?

76. What is scan chain?

77. What is scan chain reordering?

78. What is parasitic extraction?

79. What is delay calculation?

80. What is back annotation?

81. What kind of signal integrity problems do place and route tools handle?

82. What is cross-talk delay?

83. What is cross-talk noise?

84. What is IR drop?

85. What are the major netlist formats for design representation?

86. What is gate-level logic verification before tapeout?

87. What is equivalence check?

88. What is timing verification?

89. What is design constraint?

90. What is static timing analysis (STA)?

91. What is simulation approach on timing verification?

92. What is the logical-effort-based timing closure approach?

93. What is physical verification?

94. What are design rule check (DRC), design verification (DV) and geometry verification (GV)?

95. What is schematic verification (SV) or layout versus schematic (LVS)?

96. What is automatic test pattern generation (ATPG)?

97. What is tapeout?

98. What is yield?

99. What are the qualities of a good IC implementation designer?





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  • Anonymous

    Posted November 28, 2007

    A reviewer

    This is a great book for everyone who is currently involved or interested in chip design/implementation/verification/manufacture business. The book primarily focuses on concepts, not mathematic formulas. Concepts are the foundation. Without correct concepts in one's knowledge base, it is difficult to truly understand what is really going on behind the tools you are dealing with everyday, it is difficult to advance in any technical field (especially in this ultra-complicated chip design business). The intention of this book is 'broad' not necessarily 'deep'. The goal is to introduce all the key concepts needed to build up the foundation. To get involved deeper in any of the topics, the reader is equipped with basic knowledge so that he/she can consult more specialized resources (conference paper, journal paper, special-topic book, tool manual, datasheet, etc.) The unique features of this book: a) covering very board areas of IC design. It is a good reference source when someone needs an overview of this field. b) organizing in the question and answer fashion, needed information can be located quickly. Audience: a. IC integration engineer with several years' experience needs to see bigger picture, needs to expend his knowledge base, for further advance. b. IC circuit designer (transistor-level circuit designer, analog component designer and etc.) who needs to know what is going on in SoC integration area. c. IC testing engineer, product engineer, CAD support engineer who want to know more about chip development process. d. Process development researcher/engineer who wants to know what is happening in design. e. Project/business/marketing manager who needs the overview of this field, needs to know what is going on within design team (so that they can understand why 'over-budget, behind-schedule' always happens :)). f. University/college students (graduate student level) who want to pursuit career in the field of IC design. (The courses offered by universities usually focus on the basic knowledge and techniques needed for circuit design. There is hardly anything for large chip implementation.) g. Anyone who is interesting in knowing what is going on in the field of IC design. A book worth your money!

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