VLSI Design for Video Coding: H.264/AVC Encoding from Standard Specification to Chip / Edition 1

VLSI Design for Video Coding: H.264/AVC Encoding from Standard Specification to Chip / Edition 1

by Youn-Long Steve Lin, Chao-Yang Kao, Hung-Chih Kuo, Jian-Wen Chen
     
 

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VLSI Design for Video Coding

By:

Youn-Long Lin

Chao-Yang Kao

Jian-Wen Chen

Hung-Chih Kuo

High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the

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Overview

Back Cover Copy

VLSI Design for Video Coding

By:

Youn-Long Lin

Chao-Yang Kao

Jian-Wen Chen

Hung-Chih Kuo

High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing.

This book presents VLSI architectural design and chip implementation for high definition H.264/AVC video encoding with a complete FPGA prototype. It serves as an invaluable reference for anyone interested in VLSI design for video coding.

• Presents state-of-the-art VLSI architectural design and chip implementation for high definition H.264/AVC video encoding;

• Employs massively parallel processing to deliver 1080pHD, with efficient design that can be prototyped via FPGA;

• Every subsystem is presented from standard specification, algorithmic description, design considerations, timing planning, block diagram to test-bench verification;

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Product Details

ISBN-13:
9781441909589
Publisher:
Springer US
Publication date:
02/12/2010
Edition description:
2010
Pages:
176
Product dimensions:
6.40(w) x 9.30(h) x 0.70(d)

Table of Contents

1 Introduction to Video Coding and H.264/AVC 1

1.1 Introduction 1

1.1.1 Basic Coding Unit 2

1.1.2 Video Encoding Flow 2

1.1.3 Color Space Conversion 2

1.1.4 Prediction of a Macroblock 3

1.1.5 Intraframe Prediction 4

1.1.6 Interframe Prediction 4

1.1.7 Motion Vector 4

1.1.8 Prediction Error 4

1.1.9 Space-Domain to Frequency-Domain Transformation of Residual Error 5

1.1.10 Coefficient Quantization 5

1.1.11 Reconstruction 5

1.1.12 Motion Compensation 5

1.1.13 Deblocking Filtering 6

1.2 Book Organization 6

2 Intra Prediction 11

2.1 Introduction 11

2.1.1 Algorithm 12

2.1.2 Design Consideration 16

2.2 Related Works 19

2.2.1 Prediction Time Reduction Approaches 19

2.2.2 Hardware Area Reduction Approaches 19

2.3 A VLSI Design for Intra Prediction 20

2.3.1 Subtasks Scheduling 20

2.3.2 Architecture 24

2.3.3 Evaluation 30

2.4 Summary 30

3 Integer Motion Estimation 31

3.1 Introduction 31

3.1.1 Algorithms 33

3.1.2 Design Considerations 36

3.2 Related Works 37

3.2.1 Architecture 37

3.2.2 Data-Reuse Schemes 43

3.3 A VLSI Design for Integer Motion Estimation 44

3.3.1 Proposed Data-Reuse Scheme 45

3.3.2 Architecture 47

3.3.3 Data Flow 49

3.3.4 Evaluation 52

3.4 Summary 53

4 Fractional Motion Estimation 57

4.1 Introduction 57

4.1.1 Algorithms 58

4.1.2 Design Considerations 61

4.2 Related Works 61

4.3 A VLSI Design for Fractional Motion Estimation 63

4.3.1 Proposed Architecture 63

4.3.2 Proposed Resource Sharing Method for SATD Generator 68

4.3.3 Evaluation 72

4.4 Summary 72

5 Motion Compensation 73

5.1 Introduction 73

5.1.1 Algorithms 73

5.1.2 Design Considerations 75

5.2 Related Works 75

5.2.1 Memory Traffic Reduction 76

5.2.2 Interpolation Engine 76

5.3 A VLSI Design for Motion Compensation 77

5.3.1 Motion Vector Generator 77

5.3.2 Interpolator 79

5.3.3 Evaluation 83

5.4 Summary 83

6 Transform Coding 85

6.1 Introduction 85

6.1.1 Algorithms 85

6.1.2 Design Consideration 97

6.2 Related Works 97

6.2.1 Multitransform Engine Approaches 97

6.2.2 Trans/Quan or InvQuan/InvTrans Integration Approaches 97

6.3 A VLSI Design for Transform Coding 98

6.3.1 Subtasks Scheduling 98

6.3.2 Architecture 98

6.3.3 Evaluation 106

6.4 Summary 106

7 Deblocking Filter 107

7.1 Introduction 107

7.1.1 Deblocking Filter Algorithm 108

7.1.2 Subtasks Processing Order 112

7.1.3 Design Considerations 113

7.2 Related Works 115

7.3 A VLSI Design for Deblocking Filter 116

7.3.1 Subtasks Scheduling 116

7.3.2 Architecture 116

7.3.3 Evaluation 122

7.4 Summary 124

8 CABAC Encoder 125

8.1 Introduction 125

8.1.1 CABAC Encoder Algorithm 125

8.1.2 Subtasks Processing Order 134

8.1.3 Design Consideration 134

8.2 Related Works 136

8.3 A VLSI Design for CABAC Encoder 139

8.3.1 Subtasks Scheduling 139

8.3.2 Architecture 140

8.3.3 Evaluation 147

8.4 Summary 148

9 System Integration 151

9.1 Introduction 151

9.1.1 Algorithm 151

9.1.2 Design Consideration 153

9.2 Related Works 155

9.3 A VLSI Design for H.264/AVC Encoder 156

9.3.1 Subtasks Scheduling 156

9.3.2 Architecture 159

9.3.3 Evaluation 165

9.4 Summary 166

References 167

Index 173

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