VLSI for Neural Networks and Artificial Intelligence

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Product Details

  • ISBN-13: 9780306447228
  • Publisher: Basic Books
  • Publication date: 9/28/1994
  • Pages: 336
  • Product dimensions: 6.78 (w) x 10.02 (h) x 0.86 (d)

Table of Contents

Analog VLSI Neural Learning Circuits - A Tutorial 1
An Analog CMOS Implementation of a Kohonen Network with Learning Capability 25
Back-Propagation Learning Algorithms for Analog VLSI Implementation 35
An Analog Implementation of the Boltzmann Machine with Programmable Learning Algorithms 45
A VLSI Design of the Minimum Entropy Neuron 53
A Multi-Layer Analog VLSI Architecture for Texture Analysis Isomorphic to Cortical Cells in Mammalian Visual System 61
A VLSI Pipelined Neuroemulator 71
A Low Latency Digital Neural Network Architecture 81
MANTRA: A Multi-Model Neural-Network Computer 93
SPERT: A Neuro-Microprocessor 103
Design of Neural Self-Organization Chips for Semantic Applications 109
VLSI Implementation of a Digital Neural Network with Reward-Penalty Learning 119
Asynchronous VLSI Design for Neural System Implementation 129
VLSI-Implementation of Associative Memory Systems for Neural Information Processing 141
A Dataflow Approach for Neural Networks 151
A Custom Associative Chip Used as a Building Block for a Software Reconfigurable Multi-Network Simulator 159
Parallel Implementation of Neural Associative Memories on RISC Processors 167
Reconfigurable Logic Implementation of Memory-Based Neural Networks: A Case Study of the CMAC Network 177
A Cascadable VLSI Design for GENET 187
Parametrised Neural Network Design and Compilation into Hardware 197
Knowledge Processing in Neural Architecture 207
Two Methods for Solving Linear Equations Using Neural Networks 217
Hardware Support for Data Parallelism in Production Systems 231
SPACE: Symbolic Processing in Associative Computing Elements 243
PALM: A Logic Programming System on a Highly Parallel Architecture 253
A Distributed Parallel Associative Processor (DPAP) for the Execution of Logic Programs 265
Performance Analysis of a Parallel VLSI Architecture for Prolog 275
A Prolog VLSI System for Real Time Applications 285
An Extended WAM Based Architecture for OR-Parallel Prolog Execution 297
Architecture and VLSI Implementation of a Pegasus-II Prolog Processor 307
Contributors 317
Index 319
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