Wafer-Level Testing and Test During Burn-In for Integrated Circuits

by Sudarshan Bahukudumbi, Krishnendu Chakrabarty

Overview

Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this unique book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions.

Product Details

ISBN-13:	9781608076000
Publisher:	Artech House, Incorporated
Publication date:	02/01/2010
Sold by:	Barnes & Noble
Format:	eBook
File size:	9 MB

About the Author

Sudarshan Bahukudumbi is a quality and reliability test engineer at Intel Corporation. He has written several articles in peer-reviewed journals and is a frequent presenter at industry conferences. He holds an M.S. and Ph.D. in electrical engineering from New Mexico University and Duke University, respectively. Krishnendu Chakrabarty is a professor in the Department of Electrical and Computer Engineering at Duke University, North Carolina. He is the author or coauthor of six books in the IC field. He received his Ph.D. in computer science and engineering from the University of Michigan.

Table of Contents

Introduction
Wafer-Level Test and Burn-In: Industry Practices and Trends
Resource-Constrained Testing of Core-Based ScCs
Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs
Wafer-Level Test During Burn-In: Test Scheduling for Core-Based SoCs
Wafer-Level Test During Burn-In: Power Management by Test-Pattern Ordering
Wafer-Level Test During Burn-In: Power Management by Test-Pattern Manipulation
Conclusions