Title: Principles of Verifiable RTL Design: A functional coding style supporting verification processes in Verilog, Author: Lionel Bening
Title: Digital Design with Verilog® HDL: (Formerly titled Hardware Modeling with Verilog HDL), Author: Elizer Sternheim
Title: Computer Arithmetic and Verilog HDL Fundamentals, Author: Joseph Cavanagh
Title: VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on a Large RISC Processor Design, Author: Ulrich Golze

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