Title: Digital Timing Macromodeling for VLSI Design Verification / Edition 1, Author: Jeong-Taek Kong
Title: Analog Design Issues in Digital VLSI Circuits and Systems: A Special Issue of Analog Integrated Circuits and Signal Processing, An International Journal Volume 14, Nos. 1/2 (1997) / Edition 1, Author: Juan J. Becerra
Title: VLSI-SOC: From Systems to Chips: IFIP TC 10/WG 10.5, Twelfth International Conference on Very Large Scale Ingegration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany / Edition 1, Author: Manfred Glesner
Title: Systematic Design of Analog IP Blocks / Edition 1, Author: Jan Vandenbussche
Title: Electrothermal Analysis of VLSI Systems / Edition 1, Author: Yi-Kan Cheng
Title: Algorithms for VLSI Design Automation / Edition 1, Author: Sabih H. Gerez
Title: Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics / Edition 1, Author: Robert K. Brayton
Title: Low-Power Design of Nanometer FPGAs: Architecture and EDA, Author: Hassan Hassan
Title: System on Chip Design Languages: Extended papers: best of FDL'01 and HDLCon'01 / Edition 1, Author: Anne Mignotte
Title: Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard / Edition 1, Author: Nicola Nicolici
Title: Semiconductor Materials and Process Technology Handbook, Author: Gary F. McGuire
Title: From Frequency to Time-Average-Frequency: A Paradigm Shift in the Design of Electronic Systems / Edition 1, Author: Liming Xiu
Title: Timing / Edition 1, Author: Sachin Sapatnekar
Title: Switch-Level Timing Simulation of MOS VLSI Circuits / Edition 1, Author: Vasant B. Rao
Title: Parallel Algorithms and Architectures for DSP Applications / Edition 1, Author: Magdy A. Bayoumi
Title: Multi-Level Simulation for VLSI Design / Edition 1, Author: D.D. Hill
Title: Unified Methods for VLSI Simulation and Test Generation / Edition 1, Author: Kwang-Ting (Tim) Cheng
Title: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings / Edition 1, Author: Vassilis Paliouras
Title: Timing Optimization Through Clock Skew Scheduling / Edition 1, Author: Ivan S. Kourtev
Title: Correct Hardware Design and Verification Methods: 13th IFIP WG 10.5Advanced Research, Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings / Edition 1, Author: Dominique Borrione

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