ISBN-10:
0534954103
ISBN-13:
9780534954109
Pub. Date:
08/26/1996
Publisher:
CL Engineering
Analysis and Design of Digital Systems with VHDL / Edition 1

Analysis and Design of Digital Systems with VHDL / Edition 1

by Allen Dewey

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Overview

Analysis and Design of Digital Systems with VHDL / Edition 1


Dewey presents digital engineering concepts and systems in the context of a top-down design process that moves from concept to realization using specific, step-by-step procedures. In other words, Dewey introduces and explains digital concepts and systems in the first three Parts of the book, and then demonstrates how VHDL is used to model these concepts and systems in the latter three Parts. As a result, this dual-track presentation helps readers build a critical new skill set increasingly required in industry - using a hardware description language (VHDL) to specify digital systems in formats that powerful computer-based design automation programs can process quickly, making design of complex digital systems easier and faster.

Product Details

ISBN-13: 9780534954109
Publisher: CL Engineering
Publication date: 08/26/1996
Edition description: New Edition
Pages: 704
Product dimensions: 8.31(w) x 10.40(h) x 1.24(d)

Table of Contents


PREFACE 1. INTRODUCTION Electronic Systems / Digital Systems / Digital System Design Process / Design Automation / VHDL / Summary 2. REPRESENTING INFORMATION Representing Positive Numbers in Binary / Converting Between Binary and Decimal / Binary Arithmetic / Representing Negative Numbers in Binary / Octal and Hexadecimal Number Systems / Binary Codes / Representing Characters in Binary / Summary / Problems PART I: DIGITAL ENGINEERING: COMBINATIONAL SYSTEMS 3. COMBINATIONAL SYSTEMS: DEFINITION AND ANALYSIS Overview of Combinational Systems / Switching Algebra / Additional Logic Operations / Logic Mnemonics / Minimal Sets of Logic Operators / Multi-Input Logic Operator / Combinational System Analysis / Logic Expressions / Documenting Combinational Systems / Combinational System Analysis: A Second Look / Summary / Problems 4. COMBINATIONAL DESIGN: SYNTHESIS Generating Logic Expressions from Prose / Minimization Techniques / Algebraic Minimization Technique / Karnaugh Map Minimization Technique / Quine-McCluskey Minimization Technique / Exercise: Weather Vane / Summary / Problems 5. COMBINATIONAL DESIGN: IMPLEMENTATION Specification Versus Implementation / Two-Level Networks / Multilevel Networks / Multiplexers / Decoders / Memory / Programmable Logic Devices / Design Practices / Summary / Problems PART II: DIGITAL ENGINEERING: MANUFACTURING TECHNOLOGIES 6. LOGIC FAMILIES Electrical Signals and Logic Conventions / Metal-Oxide-Semiconductor Logic Families / Bipolar Logic Families / BiCMOS Logic Family / Electrical Characteristics / Summary / Problems 7. INTEGRATED CIRCUITS Diode: The pn Junction / Metal-Oxide-Semiconductor Transistors / Bipolar Transistors / Fabrication and Packaging / Application-Specific Integrated Circuits (ASICs) / IC Economics / Summary / Problems PART III: DIGITAL ENGINEERING: SEQUENTIAL SYSTEMS 8. SEQUENTIAL SYSTEMS: DEFINITION AND ANALYSIS Overview of Sequential Systems / Memory Devices / Literal Analysis / Symbolic Analysis / Timing Issues / Summary / Problems 9. SEQUENTIAL DESIGN: SYNTHESIS Simple Design Example / Generating State Diagrams from Prose / State Reduction / State Assignment and Encoded State Tables / Karnaugh Maps and Boolean Expressions / Exercise: Markov Speech Processor / Summary / Problems 10. SEQUENTIAL DESIGN: IMPLEMENTATION Combinational Logic / Registers / Shift Registers / Counters / Sequential Programmable Logic Devices (PLDs) / Putting It All Together / Summary / Problems PART IV: VHDL: COMBINATIONAL SYSTEMS 11. VHDL: A FIRST LOOK VHDL Presentation and Examples / Basic Language Organization / Interface / Architecture Body / Logic Operators / Concurrency / Design Units and Libraries / Summary / Problems 12. STRUCTURAL MODELING IN VHDL: PART I Example Schematic / Component and Signal Declarations / Component Instantiation Statements / Hierarchical Structures / Packages / Name Spaces and Scope / VHDL-93: Direct Design Entity Instantiation / Summary / Problems 13. DATA FLOW MODELING IN VHDL Modeling Styles / Conditional Concurrent Signal Assignment Statement / Relational Operators / Selected Concurrent Signal Assignment Statement / Data Flow and Hardware Parallelism / Alternative Operators / Summary / Problems 14. STRUCTURAL MODELING IN VHDL: PART II Port Modes and Their Proper use / Constant-Valued and Unconnected Ports / Regular Structures / Generate Statements / Unconstrained Ports / Generics and Parameterized Design Entities / Arithmetic Operators / Integer and Floating Points Literals / VHDL-93: Foreign Architectures / VHDL-93: New Structure Attribute / Summary / Problems PART V: MANUFACTURING TECHNOLOGIES 15. VHDL TECHNOLOGY INFORMATION: PART I Specifying Physical Values / Propagation Delay / Functions / VHDL-93: Pure and Impure Functions / Modeling Wired Logic / Prohibiting Wired Logic / Signals, Variables, and Constants / Summary / Problems 16. VHDL TECHNOLOGY INFORMATION: PART II Multi-Valued Logic / Enumeration Types / Arrays / VHDL-93: Bit String Literals / User-Defined Attributes / VHDL-93: Groups / Summary / Problems PART VI: VHDL: SEQUENTIAL SYSTEMS 17. DESCRIBING SYNCHRONOUS BEHAVIOR IN VHDL Latches / VHDL-93: Signal Value - Unaffected / Level-Sensitive Synchronous Behavior / Guard Expressions and Guarded Assignments / Edge-Sensitive Behavior / Predefined Signal Attributes / Setup and Hold Times / Assertions / VHDL-93: Postponed Assertions / Synchronous Machines / Resolved and Guarded Signals / Definition of Concurrent Statements / Simulation Cycle / Summary / Problems 18. ALGORITHMIC MODELING IN VHDL Describing State Machines: A First Look / Process and Waiting Statements / Variable and Sequential Signal Assignment Statements / Conditional Statements / Sequential Assertion Statement / VHDL-93: Report Statement / Iteration Statements / Procedures / Null Statement / More on Information Modeling - Types and Subtypes / File Input/Output / VHDL-93: File Input/Output / VHDL-93: SIMPLE_NAME, IMAGE, and VALUE Attributes / VHDL-93: Sequential Statement Labels / Summary / Problems 19. VHDL: A LAST LOOK Mixed Behavioral/Structural Descriptions / Configurations / Configuration Declarations / Component Configurations / Configuring Multiple Levels of Hierarchy / Configuration Specifications / VHDL-93: Configurations / Record Types / Access Types / Summary / Postscript / Problems / APPENDIX A: POWERS OF TWO / APPENDIX B: VHDL RESERVED KEYWORDS / APPENDIX C: INTRODUCTION TO SEMICONDUCTOR PHYSICS / INDEX

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