Computer Organization and Architecture / Edition 1

Computer Organization and Architecture / Edition 1

by Miles J. Murdocca
ISBN-10:
0471733881
ISBN-13:
2900471733880
Pub. Date:
12/06/2006
Publisher:
Wiley

Hardcover

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Overview

Computer Organization and Architecture / Edition 1

An accessible introduction to computer systems and architecture

Anyone aspiring to more advanced studies in computer-related fields must gain an understanding of the two parallel aspects of the modern digital computer: programming methodology and the underlying machine architecture. The uniquely integrated approach of Computer Architecture and Organization connects the programmer's view of a computer system with the associated hardware and peripheral devices, providing a thorough, three-dimensional view of what goes on inside the machine.

Covering all the major topics normally found in a first course in computer architecture, the text focuses on the essentials including the instruction set architecture (ISA), network-related issues, and programming methodology. Using "real world" case studies to put the information into perspective, the chapters examine:
* Data representation
* Arithmetic
* The instruction set architecture
* Datapath and Control
* Languages and the machine
* Memory
* Buses and peripherals
* Networking and communication
* Advanced computer architecture

A valuable feature of this book is the use of ARC, a subset of the SPARC processor, for an instruction set architecture. A platform-independent ARCTools suite, containing an assembler and simulator for the ARC ISA, that supports the examples used in the book is available. Better yet, the content is supplemented by online problem sets available through WileyPlus.

Balanced and thoughtfully designed for use as either a classroom text or self-study guide, Computer Architecture and Organization: An Integrated Approach will put you solidlyon track for advancing to higher levels in computer-related disciplines.

About the Author:

MILES MURDOCCAserves as the President and CEO of Internet Institute USA (IIUSA), a private postsecondary information technology (IT) school specializing in networking, operating systems, IP telephony, programming, and security. Previously, Dr. Murdocca has been a computer science faculty member at Rutgers University and a research scientist at AT&T Bell Laboratories working in computer architecture, networking, and digital optical computing. He is the author of A Digital Design Methodology for Optical Computing and Principles of Computer Architecture and a contributing author to Computer Systems Design and Architecture, Second Edition as well as the author of dozens of professional papers and patents relating to information technology.

VINCE HEURING is an associate professor and acting chair of the Department of Electrical and Computer Engineering at the University of Colorado at Boulder. He has been at the university since 1984, and prior to that he spent three years at the University of Cincinnati. Professor Heuring's research encompasses computer architectures and programming language design implementation. He and his colleague, Harry Jordan, designed and built the world's first stored program optical computer, "SPOC."

Product Details

ISBN-13: 2900471733880
Publisher: Wiley
Publication date: 12/06/2006
Series: Wiley Series in Electrical and Computer Engineering
Edition description: New Edition
Pages: 544
Product dimensions: 6.50(w) x 1.50(h) x 9.50(d)

About the Author

MILES MURDOCCAserves as the President and CEO of Internet Institute USA (IIUSA), a private postsecondary information technology (IT) school specializing in networking, operating systems, IP telephony, programming, and security. Previously, Dr. Murdocca has been a computer science faculty member at Rutgers University and a research scientist at AT&T Bell Laboratories working in computer architecture, networking, and digital optical computing. He is the author of A Digital Design Methodology for Optical Computing and Principles of Computer Architecture and a contributing author to Computer Systems Design and Architecture, Second Edition as well as the author of dozens of professional papers and patents relating to information technology.

VINCE HEURING is an associate professor and acting chair of the Department of Electrical and Computer Engineering at the University of Colorado at Boulder.  He has been at the university since 1984, and prior to that he spent three years at the University of Cincinnati.  Professor Heuring’s research encompasses computer architectures and programming language design implementation. He and his colleague, Harry Jordan, designed and built the world’s first stored program optical computer, “SPOC.”

Table of Contents


Preface     ix
Introduction     1
A Brief History of Computing     1
The Von Neumann Model     9
The System Bus Model     10
Levels of Machines     11
Upward Compatibility     12
The Levels     12
A Typical Computer System     16
Role of the Network     18
Organization of the Book     20
Case Study: What Happened to Supercomputers?     20
Data Representation     27
Fixed-Point Numbers     28
Range and Precision in Fixed-Point Numbers     28
The Associative Law of Algebra Does Not Always Hold in Computers     29
Radix Number Systems     29
Conversions Among Radices     30
An Early Look at Computer Arithmetic     35
Signed Fixed-Point Numbers     36
Floating-Point Numbers     40
Range and Precision in Floating-Point Numbers     40
Normalization and the Hidden Bit     41
Representing Floating-Point Numbers in the Computer-Preliminaries     42
Error in Floating-Point Representations     44
The IEEE 754 Floating-Point Standard     47
Case Study: Patriot Missile Defense FailureCaused by Loss of Precision     51
Character Codes     52
The ASCII Character Set     53
The EBCDIC Character Set     54
The Unicode Character Set     56
Arithmetic     61
Fixed-Point Addition and Subtraction     61
Two's Complement Addition and Subtraction     61
Sign Extension     64
Hardware Implementation of Adders and Subtractors     65
One's Complement Addition and Subtraction     67
Fixed-Point Multiplication and Division     68
Unsigned Multiplication     69
Unsigned Division     70
Signed Multiplication and Division     73
Floating-Point Arithmetic     73
Floating-Point Addition and Subtraction     73
Floating-Point Multiplication and Division     76
High-Performance Arithmetic     77
High-Performance Addition     77
High-Performance Multiplication     81
High-Performance Division     84
Residue Arithmetic     86
The Instruction Set Architecture     93
Hardware Components of the Instruction Set Architecture     93
The System Bus Model Revisited     94
Memory      94
The CPU     98
ARC, A RISC Computer     102
ARC Memory     103
ARC Registers     103
ARC Assembly Language Format     105
The ARC Instruction Set     109
ARC Instruction Formats     112
SPARC and ARC Data Formats     114
ARC Instruction Descriptions     114
Pseudo-Operations     123
Synthetic Instructions     125
Examples of Assembly Language Programs     125
Variations in Machine Architectures and Addressing     128
Performance of Instruction Set Architectures     131
Accessing Data in Memory-Addressing Modes     131
Subroutine Linkage and Stacks     132
Input and Output in Assembly Language     137
Case Study: The Java Virtual Machine ISA     140
Datapath and Control     151
Basics of the Microarchitecture     151
The Datapath     152
Datapath Overview     153
The Control Section-Microprogrammed     160
Timing     164
Developing the Microprogram     164
Traps and Interrupts     172
Nanoprogramming     175
The Control Section-Hardwired     176
Case Study: The VHDL Hardware Description Language     183
Background     183
What is VHDL?     184
A VHDL Specification of the Majority Function     185
Nine-Value Logic System     188
Case Study: What Happens When a Computer Boots Up?     188
Languages and the Machine     197
The Compilation Process     197
Steps in Compilation     197
The Compiler Mapping Specification     198
How the Compiler Maps the Three Instruction Classes into Assembly Code     199
Data Movement     200
Arithmetic Instructions     203
Program Control Flow     203
The Assembly Process     205
Assembly and Two-Pass Assemblers     206
Assembly and the Symbol Table     209
Final Tasks of the Assembler     211
Programs for Embedded vs. Virtual Memory Systems     211
Linking and Loading     213
Linking     213
Resolving External References     214
Loading     216
Macros     217
Quantitative Analyses of Program Execution     224
Quantitative Performance Analysis      226
From CISC to RISC     227
Pipelining the Datapath     229
Arithmetic, Branch, and Load-Store Instructions     229
Pipelining Instructions     231
Keeping the Pipeline Filled     231
Overlapping Register Windows     234
Low-Power Coding     241
Memory     249
The Memory Hierarchy     249
Random-Access Memory     250
Memory Chip Organization     252
Constructing Large RAMs From Small RAMs     255
Commercial Memory Modules     256
Read-Only Memory     257
Flash Memory     260
Case Study: Rambus Memory     262
Cache Memory     266
Associative Mapped Cache     267
Direct-Mapped Cache     270
Set-Associative Mapped Cache     273
Cache Performance     274
Hit Ratios and Effective Access Times     276
Multilevel Caches     277
Cache Management     279
Cache Coherency     280
Virtual Memory     281
Overlays     281
Paging     282
Segmentation     286
Protection      288
Fragmentation     288
The Translation Lookaside Buffer     290
Putting It All Together     291
Advanced Topics     292
Content-Addressable (Associative) Memories     292
Case Study: Associative Memory in Routers     295
Case Study: The Intel Pentium 4 Memory System     297
Buses and Peripherals     303
Parallel Bus Architectures     304
Bus Structure, Protocol, and Control     304
Bus Clocking     305
The Synchronous Bus     306
The Asynchronous Bus     307
Bus Arbitration-Masters and Slaves     308
Bridge-Based Bus Architectures     310
Internal Communication Methodologies     311
Programmed I/O     312
Interrupt-Driven I/O     313
Direct Memory Access (DMA)     314
Case Study: Communication on the Intel Pentium Architecture     316
System Clock, Bus Clock, and Bus Speeds     316
Address, Data, Memory, and I/O Capabilities     316
Data Words Have Soft Alignment     317
Bus Cycles in the Pentium family     317
Memory Read and Write Bus Cycles     318
The Burst Read Bus Cycle      319
Bus Hold for Request by Bus Master     320
Data Transfer Rates     321
Serial Bus Architectures     321
RS-232     322
Universal Serial Bus (USB)     322
Firewire     323
Mass Storage     323
Magnetic Disks     323
Magnetic Tape     330
Optical Disks     332
RAID-Redundant Arrays of Inexpensive Disks     334
Input Devices     339
Keyboards     339
Tablets     339
Mice and Trackballs     340
Touch-Sensitive Pen-Based Display     341
Joysticks     342
Output Devices     342
Laser Printers     342
Video Displays     343
Liquid Crystal Displays (LCDs)     345
Case Study: Graphics Processing Unit     346
Case Study: How a Virus Infects a Machine     347
Networking and Communication     353
A Few Modulation Schemes     353
Transmission Media     355
Two-Wire Open Lines     356
Twisted-Pair Lines     356
Coaxial Cable     357
Optical Fiber     357
Satellites      358
Terrestrial Microwave     358
Radio     359
Error Detection and Correction     359
Bit Error Rate Defined     360
Hamming Codes     360
Vertical Redundancy Checking     365
Cyclic Redundancy Checking     366
Networking and Network Device Architectures     368
The OSI Model     368
Topologies     370
Ethernet     371
Hubs, Bridges, Switches, Routers, and Gateways     376
Storage Area Networks     378
Case Study: Cisco Router Architecture     379
Advanced Computer Architecture     385
Parallel Architecture     385
Measuring Performance     386
The Flynn Taxonomy     387
Interconnection Networks     388
Mapping an Algorithm Onto a Parallel Architecture     393
Superscalar Machines and the PowerPC     398
Instruction Set Architecture of the PowerPC     399
Hardware Architecture of the PowerPC     399
VLIW Machines, and the Itanium     401
Case Study: The Intel IA-64 (Itanium) Architecture     402
Background-the 80x86 CISC Architecture     402
The Itanium: an Epic Architecture     402
Case Study: Extensions to the Instruction Set-The Intel MMX/SSEX and Motorola AltiVec SIMD Instructions     406
Background     407
The Base Architectures     407
VECTOR Registers     408
Vector Arithmetic Operations     410
Vector Compare Operations     411
Case Study Summary     412
Programmable Logic Devices and Custom ICs     413
The Role of CAD Tools in PLD Design     414
PLAS and PALS     414
Complex Programmable Logic Devices     415
Field-Programmable Gate Arrays     415
Application-Specific Integrated Circuits     416
Unconventional Architectures     417
DNA Computing     417
Quantum Computing     419
Multi-valued Logic     420
Neural Networks     422
Digital Logic     429
Introduction     429
Combinational Logic     429
Truth Tables     430
Logic Gates     431
Electronic Implementation of Logic Gates     434
Tri-State Buffers     437
Properties of Boolean Algebra     438
The Sum-of-Products Form and Logic Diagrams      440
The Product-of-Sums Form     442
Positive vs. Negative Logic     443
The Data Sheet     445
Digital Components     447
Levels of Integration     447
Multiplexers     447
Demultiplexers     449
Decoders     450
Priority Encoders     452
Programmable Logic Arrays     453
Sequential Logic     457
The S-R Flip-Flop     457
The Clocked S-R Flip-Flop     459
The D Flip-Flop and the Master-Slave Configuration     460
J-K and T Flip-Flops     462
Design of Finite State Machines     464
Mealy vs. Moore Machines     471
Registers     472
Counters     474
Reduction of Combinational Logic and Sequential Logic     474
Reduction of Two-Level Expressions     475
The Algebraic Method     475
The K-Map Method     476
The Tabular Method     481
Logic Reduction: Effect on Speed and Performance     488
State Reduction     492
Using ARCTools     505
Introduction     505
Accessing and Launching ARCTools      505
Launching ARCTools     506
The ARC Assembler     506
Loading, Assembling, and Examining a File     508
Saving Files     510
Loading Files into the Simulator     510
The ARC Simulator     510
Instructions and Pseudo Instructions Recognized by ARCTools     512
Instructions-Actual, Synthetic, and Pseudo     512
The Macroprocessor     514
Measuring Program Performance     514
The TimeModel configuration Editor     515
Memory/IO Parameters     516
TimeModel's Statistics Window     516
The Cache Simulator View     517
Index     519

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