CMOS Processors and Memories

CMOS Processors and Memories

by Krzysztof Iniewski (Editor)


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Product Details

ISBN-13: 9789400733046
Publisher: Springer Netherlands
Publication date: 10/13/2012
Series: Analog Circuits and Signal Processing
Edition description: 2010
Pages: 382
Product dimensions: 6.10(w) x 9.25(h) x 0.03(d)

About the Author

Krzysztof (Kris) Iniewski is managing R&D at Redlen Technologies Inc., a start-up company in British Columbia. His research interests are in VLSI circuits for medical and security applications. He is also an executive director of CMOS Emerging Technologies ( From 2004 to 2006 he was an Associate Professor at the Electrical Engineering and Computer Engineering Department of University of Alberta where he conducted research on low power wireless circuits and systems. During his tenure in Edmonton he put together a book for CRC Press "Wireless Technologies: Circuits, Systems and Devices".
From 1995 to 2003, he was with PMC-Sierra and held various senior technical and management positions. Prior to joining PMC-Sierra, from 1990 to 1994 he was an Assistant Professor at the University of Toronto’s Electrical Engineering and Computer Engineering. Dr. Iniewski has published over 100 research papers in international journals and conferences. He holds 18 international patents granted in USA, Canada, France, Germany, and Japan. He received his Ph.D. degree in electronics (honors) from the Warsaw University of Technology (Warsaw, Poland) in 1988. Together with Carl McCrosky and Dan Minoli he is an author of "Data Networks – VLSI and Optical Fibre", Wiley, 2008. He recently edited "Medical Imaging Electronics", Wiley 2009, "VLSI Circuits for Bio-medical applications", Artech House 2008, and "Circuits at Nanoscale: Communications, Imaging and Sensing", CRC Press 2008.

Table of Contents

Part I Processors.
Chapter 1. Design of High Performance Low Power Processors; Umesh Nawathe. Chapter 2. Towards high-performance and energy-efficient multi-core processors; Zhiyi Yu. Chapter 3. Low Power Asynchronous Circuit Design – An FFT/IFFT Processor; Gwee Bah Hwee and Kwen-Siong Chong. Chapter 4. CMOL/CMOS Implementations of Bayesian Inference Engine - Digital and Mixed-Signal Architectures and Performance/Price -A Hardware Design Space Exploration; Dan Hammerstorm and Mazad S. Zaveri. Chapter 5. A Hybrid CMOS-Nano FPGA Based on Majority Logic: From Devices to Architecture; Garrett S. Rose and Harika Manem.

Part II Memories.
Chapter 6. Memory Systems for Nano-Computer (CMOS Nanoelectronics); Yong Hoon Kang. Chapter 7. Flash Memories; Taku Ogura. Chapter 8. CMOS-based Spin-Transfer Torque Magnetic Random Access Memory (ST-MRAM); Byoung C. Choi, Y.K. Hong, A. Lyle, and G.W. Donohoe. Chapter 9. Magnetization Switching in Spin Torque Random Access Memory: Challenges and Opportunities; Xiaobin Wang, Yiran Chen and Tong Zhang. Chapter 10. High Performance Embedded Dynamic Random Access Memory in Nano-Scale Technologies; Toshiaki Kirihata. Chapter 11. Timing Circuit Design in High Performance DRAM; Feng (Dan) Lin. Chapter 12. Overview and Scaling Prospect of Ferroelectric Memories; Daisaburo Takashima.

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