ISBN-10:
1498772714
ISBN-13:
9781498772716
Pub. Date:
12/02/2016
Publisher:
Taylor & Francis
Computer Architecture: Fundamentals and Principles of Computer Design, Second Edition / Edition 2

Computer Architecture: Fundamentals and Principles of Computer Design, Second Edition / Edition 2

by Joseph D. Dumas II

Hardcover

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Product Details

ISBN-13: 9781498772716
Publisher: Taylor & Francis
Publication date: 12/02/2016
Edition description: Revised
Pages: 462
Product dimensions: 6.30(w) x 9.30(h) x 1.20(d)

About the Author

Joe Dumas earned his Ph.D. in Computer Engineering from the University of Central Florida in 1993, where he also received the first Link Foundation Fellowship in Advanced Simulation and Training. Previously, he earned the M.S. degree in Electrical Engineering from Mississippi State University in 1989 and the B.S. degree in Electronics Engineering Technology, with a minor in Computer Science, from the University of Southern Mississippi in 1984.

Dr. Dumas is a faculty member in the University of Tennessee at Chattanooga’s College of Engineering and Computer Science, where he holds the rank of UC Foundation Professor and has served as a Faculty Senator and Chair of the Graduate Council, among a number of campus leadership positions. He was chosen as Outstanding Computer Science Teacher in 1998, 2002, and 2009. Dr. Dumas’ areas of interest include computer architecture, embedded systems, virtual reality, and real-time, human-in-the-loop simulation.

Dr. Dumas is a member of several academic honor societies including Upsilon Pi Epsilon (Computer Science), Eta Kappa Nu (Electrical Engineering), Tau Beta Pi (Engineering), and Tau Alpha Pi (Engineering Technology). He was a founding member of the Chattanooga chapter of the IEEE Computer Society and served for several years as faculty advisor for the UTC student chapter of IEEE-CS. An avid downhill skier, tennis player, and distance runner with over 30 completed marathons, Joe Dumas lives in Signal Mountain, Tennessee with his wife Chereé.

Table of Contents

Contents

  • Chapter 1

Introduction to computer architecture

1.1 What is computer architecture?

1.1.1 Architecture vs. implementation

1.2 Brief history of computer systems

1.2.1 The first generation

1.2.2 The second generation

1.2.3 The third generation

1.2.4 The fourth generation

1.2.5 The fifth generation

1.2.6 Modern computing: the sixth generation

1.3 Types of computer systems

1.3.1 Single processor systems

1.3.2 Parallel processing systems

1.3.3 Special architectures

1.4 Quality of computer systems

1.4.1 Generality and applicability

1.4.2 Ease of use

1.4.3 Expandability

1.4.4 Compatibility

1.4.5 Reliability

1.5 Success and failure of computer architectures and
implementations

1.5.1 Quality and the perception of quality

1.5.2 Cost issues

1.5.3 Architectural openness, market timing, and other issues

1.6 Measures of performance

1.6.1 CPU performance

1.6.2 Memory system performance

1.6.3 I/O system performance

1.6.4 Power performance

1.6.5 System benchmarks

1.7 Chapter wrap-up

1.8 Review questions

  • Chapter 2

Computer memory systems

2.1 The memory hierarchy

2.1.1 Characteristics of an ideal memory

2.1.2 Characteristics of real memory devices

2.1.3 Hierarchical memory systems

2.2 Main memory interleaving

2.2.1 High-order interleaving

2.2.2 Low-order interleaving

2.3 Logical organization of computer memory

2.3.1 Random access memories

2.3.2 Sequential access memories

2.3.3 Associative memories

2.4 Cache memory

2.4.1 Locality of reference

2.4.2 Hits, misses, and performance

2.4.3 Mapping strategies

2.4.4 Cache write policies

2.4.5 Cache replacement strategies

2.4.6 Cache initialization

2.5 Memory management and virtual memory

2.5.1 Why virtual memory?

2.5.2 Virtual memory basics

2.5.3 Paged virtual memory

2.5.4 Segmented virtual memory

2.5.5 Segmentation with paging

2.5.6 The MMU and TLB

2.5.7 Cache and virtual memory

2.6 Chapter wrap-up

2.7 Review questions

  • Chapter 3

Basics of the central processing unit

3.1 The instruction set

3.1.1 Machine language instructions

3.1.2 Functional categories of instructions

3.1.3 Instruction addressing modes

3.1.4 Number of operands per instruction

3.1.5 Memory-register vs. load-store architectures

3.1.6 CISC and RISC instruction sets

3.2 The datapath

3.2.1 The register set

3.2.2 Integer arithmetic hardware

3.2.2.1 Addition and subtraction

3.2.2.2 Multiplication and division

3.2.3 Arithmetic with real numbers

3.2.3.1 Why use floating-point numbers?

3.2.3.2 Floating-point representation

3.2.3.3 Floating-point arithmetic hardware

3.3 The control unit

3.3.1 A simple example machine

3.3.2 Hardwired control unit

3.3.3 Microprogrammed control unit

3.4 Chapter wrap-up

3.5 Review questions

  • Chapter 4

Enhancing CPU performance

4.1 Pipelining

4.2 Arithmetic pipelines

4.3 Instruction unit pipelines

4.3.1 Basics of an instruction pipeline

4.3.2 Control transfers and the branch penalty

4.3.3 Branch prediction

4.3.4 Delayed control transfers

4.3.5 Memory accesses: delayed loads and stores

4.3.6 Data dependencies and hazards

4.3.7 Controlling instruction pipelines

4.4 Characteristics of RISC machines

4.5 Enhancing the pipelined CPU

4.5.1 Superpipelined architectures

4.5.2 Superscalar architectures

4.5.3 Very long instruction word (VLIW) architectures

4.5.4 Multithreaded architectures

4.6 Chapter wrap-up

4.7 Review questions

  • Chapter 5

Exceptions, interrupts, and input/output systems

5.1 Exceptions

5.1.1 Hardware-related exceptions

5.1.1.1 Maskable interrupts

5.1.1.2 Nonmaskable interrupts

5.1.1.3 Watchdog timers and reset

5.1.1.4 Nonvectored, vectored, and autovectored
interrupts

5.1.2 Software-related exceptions

5.2 Input and output device interfaces

5.3 Program-controlled I/O

5.3.1 Memory-mapped I/O

5.3.2 Separate I/O

5.4 Interrupt-driven I/O

5.5 Direct memory access

5.6 Input/output processors

5.7 Real-world I/O example: the universal serial bus

5.8 Chapter wrap-up

5.9 Review questions

  • Chapter 6

Parallel and high-performance systems

6.1 Types of computer systems: Flynn’s taxonomy

6.1.1 Vector and array processors

6.1.2 GPU computing

6.1.3 Multiprocessor systems

6.1.4 Multicomputer systems

6.2 Interconnection networks for parallel systems

6.2.1 Purposes of interconnection networks

6.2.2 Interconnection network terms and concepts

6.2.2.1 Master and slave nodes

6.2.2.2 Circuit switching vs. packet switching

6.2.2.3 Static and dynamic networks

6.2.2.4 Centralized control vs. distributed control

6.2.2.5 Synchronous timing vs. asynchronous timing

6.2.2.6 Node connection degree

6.2.2.7 Communication distance and diameter

6.2.2.8 Cost, performance, expandability, and
fault tolerance

6.2.3 Bus-based interconnections

6.3 Static interconnection networks

6.3.1 Linear and ring topologies

6.3.2 Star networks

6.3.3 Tree and fat tree networks

6.3.4 Nearest-neighbor mesh

6.3.5 Torus and Illiac networks

6.3.6 Hypercube networks

6.3.7 Routing in static networks

6.4 Dynamic interconnection networks

6.4.1 Crossbar switch

6.4.2 Recirculating networks

6.4.3 Multistage networks

6.4.3.1 Blocking, nonblocking, and rearrangeable
networks

6.5 Chapter wrap-up

6.6 Review questions

  • Chapter 7

Special-purpose and future architectures

7.1 Dataflow machines

7.2 Artificial neural networks

7.3 Fuzzy logic architectures

7.4 Quantum computing

7.5 Chapter wrap-up

7.6 Review questions

  • Appendix

Reference and further reading materials with
web links

Chapter 1: Introduction to computer architecture

Chapter 2: Computer memory systems

Chapter 3: Basics of the central processing unit

Chapter 4: Enhancing CPU performance

Chapter 5: Exceptions, interrupts, and input/output systems

Chapter 6: Parallel and high-performance systems

Chapter 7: Special-purpose and future architectures

Computer architecture (general)

Index

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