Pub. Date:
Basic Books
Defect and Fault Tolerance in VLSI Systems

Defect and Fault Tolerance in VLSI Systems

by Israel Koren


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Product Details

ISBN-13: 9780306432248
Publisher: Basic Books
Publication date: 01/01/1989
Pages: 378

Table of Contents

1 Yield Models for Defect-Tolerant VLSI Circuits: A Review.- 2 Wafer Scale Revisited.- 3 Models for Defects and Yield.- Defects, Faults and Semiconductor Device Yield.- On the Probability of Fault Occurrence.- A New Yield Formula for Fault-Tolerant Large Area Devices.- 4 Defect-Tolerant Designs.- Defect Tolerant Interconnects for VLSI.- Combining Architecture and Algorithm for Yield Enhancement and Fault Tolerance.- Design of a Fault-Tolerant DRAM with New On-Chip ECC.- 5 Defect Monitoring and Yield Projection.- Measurement and Distribution of Faults on Defect Test Site Chips.- Process Development and Circuit Design Interactions in VLSI Yield Improvement.- Yield Projection Based on Electrical Fault Distribution and Critical Structure Analysis.- Yield Model for Yield Projection from Test Site.- 6 Testing and Testable Designs.- Test Methods for Wafer-Scale Integration.- Fault Diagnosis of Linear Processor Arrays.- Fault Diagnosis of Array Processors with Uniformly Distributed Faults.- 7 Defect- and Fault-Tolerant Processors.- Designing for High Yield: The NS32532 Microprocessor.- Defect Tolerance in a 16 Bit Microprocessor.- Design Techniques for a Self-Checking Self-Exercising Processor.- Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors.- 8 Defect- and Fault-Tolerant Memories.- Diagnosis and Repair of Large Memories: A Critical Review and Recent Results.- A Reconfigurable SRAM 4.5 MBit WSI Memory.- Block Alignment: A Method for Increasing the Yield of Memory Chips that are Partially Good.- Fault Tolerant Integrated Memory Design.- 9 Reconfigurable Arrays.- Probabilistic Analysis of Yield and Area Utilization of Reconfigurable Rectangular Processor Arrays.- Fabrication-Time and Run-Time Fault-Tolerant Array Processors Using Single-Track Switches.- An Efficient Restructuring Approach for Wafer Scale Processor Arrays.- Orthogonal Mapping: A Reconfiguration Strategy for Fault Tolerant VLSI/WSI 2-Dimensional Arrays.- A General Model for Fault Covering Problems in Reconfigurable Arrays.- 10 Fault-Tolerant Arrays.- Defect Tolerance in a Wafer Scale Array for Image Processing.- Distributed Fault-Tolerant Embedding of Binary Trees and Rings in Hypercubes.- On the Analysis and Design of Hierarchical Fault-Tolerant Processor Arrays.- Contributors.

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