While some quantitative analysis is necessary to understand underlying concepts, tedious mathematical equations and formal proofs are avoided. An intuitive appreciation for switched-capacitor circuits is achieved.
Much of the existing information on contemporary switched-capacitor circuit applications is in the form of applications notes and data sheets for various switched-capacitor ICs. This book compiles such information in a single volume and coherently organizes and structures it.
The author has his own website at mingliangliu.com
* Step-by-step tutorials which emphasize the most fundamental principals of switched-capacitor circuits
* Few tedious mathematical equations
* The first easy-to-understand compilation on this subject--most information available is not very cohesive
|Sold by:||Barnes & Noble|
|File size:||7 MB|
Read an Excerpt
Demystifying Switched-Capacitor Circuits
By Mingliang Liu
NewnesCopyright © 2006 Elsevier Inc.
All right reserved.
Chapter OneBasic MOS Device Physics
This chapter focuses on the fundamental aspects of metal-oxide semiconductor (MOS) device behavior that are of immediate relevance to practical integrated circuit (IC) design. It is intended as a review of basic principles rather than an in-depth treatment of advanced topics.
This chapter is organized as follows. Section 1.2 describes the fundamental aspects of MOS transistors. The basic properties of MOS switches are discussed in Section 1.3. The behavior of the MOS device as a capacitor is discussed in Section 1.4.
1.2 MOS Transistors
Perhaps the most widely adopted process technologies in today's IC industry are those that use metal-oxide semiconductor (MOS) transistors. A MOS transistor can also be referred to as a metal-oxide semiconductor field-effect transistor (MOSFET). Other acronyms are MOST (for MOS transistor) and IGFET (for insulated-gate field-effect transistor). The term metal in the acronym MOS indicates that the transistor's gate is made of metallic materials such as metalsilicon. Nowadays, heavily doped polycrystalline silicon (also known as polysilicon) is usually chosen over metalsilicon because polysilicon can be aligned and scaled with higher geometric precision, resulting in smaller and faster transistors.
There are two complementary types of MOS transistors: N-channel MOS (NMOS) and P-channel MOS (PMOS). NMOS transistors use electrons to deliver charge in the presence of a positive gate voltage, while PMOS transistors use holes (which are equivalent to positive carriers) to conduct current in the presence of a negative gate voltage. Be it of NMOS or of PMOS type, each MOS transistor is a unipolar device, meaning there can be only one type of carrier (electrons for NMOS and holes for PMOS) traveling in the channel.
If a bipolar MOS device is desired, we can incorporate both NMOS and PMOS transistors onto the same monolithic chip, resulting in what is called a complementary MOS (CMOS) circuit. In practice, there are three different types of CMOS processes: local-oxidation-of-silicon (LOCOS) process, shallow-trench-isolation (STI) process, and silicon-on-insulator (SOI) process. The latter two are known for their immunities to the latch-up problem. In this book, we discuss the CMOS transistors that are realized in the LOCOS process only.
A conceptual cross-section diagram of a typical NMOS transistor implemented in a LOCOS-type CMOS process is shown in Figure 1.1.
In the NMOS transistor, the two heavily doped N+ regions are the source and the drain, respectively. They are diffused into a slightly doped semiconductor body called the P-substrate. The distance between the source and the drain is called the channel length, which is denoted as L in the diagram. It may also be referred to as the effective gate length and is typically shorter than the physical gate length. In comparison with the NMOS transistor, the PMOS transistor is normally fabricated in an N-well pocket. The N-well is not a substrate, but rather an isolated region of higher surface concentration with relatively more free carriers as compared to the P-substrate.
A layer of silicon dioxide (SiO2) is grown beneath the gate to physically isolate it from the remaining regions in the transistor. In an ideal situation, no charge is leaked from the gate into the channel. However, in reality, when a varying signal (e.g., a clock signal) is applied to the gate, a transient charge is coupled into the channel through the small-signal capacitance that resides between the gate and the channel. Additionally, the gate-source capacitance (Cgs) and the gate-drain capacitance (Cgd) result in more charge leakages. This phenomenon is called clock feedthrough, and its effect becomes more pronounced when the transistor is placed at the input of an open-loop amplifier. In such a case, the input offset caused by the charge leakage may saturate the amplifier.
Once the transistor is turned off, the residual charge stored in the channel is dispersed through the drain and the source to elsewhere in the circuit. This phenomenon is known as charge injection, which introduces signal-dependent errors to the circuit. The mechanism of charge injection is treated later in this chapter.
As shown in Figure 1.1, the source, drain, and P-substrate of the NMOS transistor are all connected to ground. When the gate voltage (Vg) is below zero (i.e., Vgs < 0), positive carriers (P+) accumulate in the region under the gate and the dioxide layer, which is called the accumulation region. When Vgs is of a sufficiently large positive value, negative carriers such as electrons take over this region and form a channel connecting the drain and source regions. In other words, the accumulation P-region doped with (P+) carriers is converted into an N-region consisting of negative carriers. Hence, the channel is inverted, and the transistor is said to be working in the inversion region.
Then the question arises: What is the minimum positive value of Vgs for which an inverted channel can be formed between the drain and the source? The appropriate response to this question leads to the threshold voltage, which is commonly denoted as Vthn (or Vthp for PMOS transistors). That is, when Vgs ≥ Vthn, the device enters into the inversion region. The result of subtracting Vthn from Vgs is usually called the effective drain-source voltage and denoted as Veff. When 0 < Vgs < Vthn, or equivalently, Veff < 0, both holes and electrons have low density levels, and the transistor is said to be operating in the depletion region.
When Vgs > Vthn, the connection between the drain and the source is formed. However, to allow current to flow from the drain to the source, the drain-source voltage (Vds) must be larger than zero. It can be shown that the drain-source current (Id) gradually increases with Vds, and for a small Vds (0.1V < Vds << Veff), the relationship between Id and Vds is given by
[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (1.1)
where µn is the electron mobility near the silicon surface (the skin effect is negligible since we assume a low frequency configuration here), Cox is the gate capacitance per unit area, W is the gate width, and L is the effective channel length. The transistor is now working in the weak inversion region. When Vds < 0.1V, the transistor is said to be working in the subthreshold region.
It can be shown that for a moderate Vds (0.5 Veff < Vds < Veff), the relationship between Id and Vds is approximately given by
[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (1.2)
The transistor is now working in the triode region. Finally, once Vds reaches Veff, the pinch-off condition is satisfied, meaning beyond this point Id remains constant (to a first-order approximation) with respect to Vds. At the pinch-off point where Vds = Veff, the resulting Id ~ Vds relationship is given by
[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (1.3)
This is known as the square-law I-V characteristic. The transistor is said to be working in the active (or saturation) region.
The transconductance (gm), which is commonly used in the small-signal model for a MOS transistor working in the active region, is defined as
[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (1.4)
In the active region, the transconductance can be obtained based on Equation (1.3)
[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (1.5)
The transconductance can also be expressed as
[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (1.6)
Interestingly, Equation (1.6) indicates that gm can be determined by the ratio of the drain current (Id) to the effective gate-source voltage (Veff). What's more, it is possible to make the transconductance be independent of the value of (W/L) as long as that ratio is kept as a constant. Hence, to a first-order approximation, the scaling of the transistor geometry does not affect gm. This is a desirable feature because the voltage gain and accuracy can be maintained while the device is being downscaled (however, this argument does not hold in submicron processes where the short-channel effects become prominent).
Also, from Equation (1.5) we realize that for a given transistor in a given process, the value of gm is controlled by the gate-source voltage (Vgs). Qualitatively speaking, this property is appropriate for analog MOS amplifiers where the linearity performance is reflected by how cohesively the intrinsic gain (i.e., gmRout, where Rout is the output impedance) tracks the change in Vgs of the MOS transistor.
In the triode region, the transconductance is obtained based on Equation (1.2),
[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (1.7)
where Vds < Veff. Since Vds is not governed by Vgs, the value of gm does not accurately reflect the change in Vgs; consequently, the linearity of the analog amplifier is degraded as compared to the situation where the transistor is operating in the active region. As a result, in many analog applications where a good linearity is required, all the MOS transistors in the signal path should operate in the active rather than the triode region. By contrast, in digital circuits that make use of MOS transistors to realize digital logic gates, linearity is usually not a concern; thus, the transistors may operate in either triode or active regions, depending on the desired logic function.
Scaling of MOS Transistors
Propelled by the nonstopping advancement of lithography and implantation technologies, the minimum feature size of a MOS transistor has been continually reduced since the 1980s, enabling the unprecedented success of digital CMOS circuits and doubling the system-on-a-chip (SOC) computing capability every 18 to 24 months, which is known as Moore's law.
In addition to a higher level of system integration and lower cost, the continual downscaling of MOS transistors brings about a significant increase in the cutoff frequency (ft) of the MOS transistor, opening an avenue to achieve high-speed/high-frequency integrated systems using a pure CMOS technology. Specifically, the cutoff frequency ft is normally defined to be the frequency at which the transistor's current gain is unity. It can be shown that ft of a typical NMOS transistor is given by the following expression:
[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (1.8)
Thus, ft is proportional to 1/L2.
Excerpted from Demystifying Switched-Capacitor Circuits by Mingliang Liu Copyright © 2006 by Elsevier Inc. . Excerpted by permission of Newnes. All rights reserved. No part of this excerpt may be reproduced or reprinted without permission in writing from the publisher.
Excerpts are provided by Dial-A-Book Inc. solely for the personal use of visitors to this web site.
Table of ContentsChapter 1 – Basic MOS Device Physics
Chapter 2 – Operational Amplifiers
Chapter 3 –Switched-Capacitor Building Blocks
Chapter 4 – Switched-Capacitor Filters
Chapter 5 – Switched-Capacitor Data Converters
Chapter 6 – Switched-Capacitor DC-DC Converters
Chapter 7 – Advanced Switched-Capacitor Circuit Techniques
Chapter 8 – Design of SC Delta-Sigma Modulators for Multi-Standard RF Receivers